Analytical threshold voltage model for short channel n+-p+ double-gate SOI MOSFET's

IEEE Transactions on Electron Devices

Volumn 43, Issue 5, 1996, Pages 732-738

  Suzuki, Kunihiro ^a,b   Tosaka, Yoshihara ^b   Sugii, Toshihiro ^b  

^a IEEE

^b FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

GATES (TRANSISTOR); MATHEMATICAL MODELS; PERMITTIVITY; SEMICONDUCTOR DOPING; SILICA; SILICON ON INSULATOR TECHNOLOGY;

FLATBAND VOLTAGE; GATE VOLTAGE; POLYSILICON GATE; THRESHOLD VOLTAGE; TWO DIMENSIONAL POISSON EQUATION;

MOSFET DEVICES;

EID: 0030150045     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.491249     Document Type: Article

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