Performance advantage of Schottky source/drain in ultrathin-body silicon-on-insulator and dual-gate CMOS

IEEE Transactions on Electron Devices

Volumn 50, Issue 5, 2003, Pages 1340-1345

  Connelly, Daniel ^a   Faulkner, Carl ^a   Grupp, D E ^a  

^a Acorn Technologies   (United States)

Author keywords

CMOSFET circuits; MOS devices; Schottky barriers; Semiconductor device modeling; Semiconductor metal interfaces; Silicon; Simulation

Indexed keywords

COMPUTER SIMULATION; GATES (TRANSISTOR); MOS DEVICES; MOSFET DEVICES; OPTIMIZATION; SCHOTTKY BARRIER DIODES; SEMICONDUCTOR DEVICE MODELS; SILICON ON INSULATOR TECHNOLOGY;

MIXED MODE SIMULATION; SEMICONDUCTOR METAL INTERFACES; ULTRATHIN SILICON TECHNOLOGIES;

CMOS INTEGRATED CIRCUITS;

EID: 0042855935     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.813229     Document Type: Article

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