15-nm-thick Si channel wall vertical double-gate MOSFET

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2002, Pages 949-951

  Masahara, Meishoku ^a   Matsukawa, Takashi ^a   Ishii, Ken Ichi ^a   Liu, Yongxun ^a   Tanoue, Hisao ^a   Sakamoto, Kunihiro ^a   Sekigawa, Toshihiro ^a   Yamauchi, Hiromi ^a   Kanemaru, Seigo ^a   Suzuki, Eiichi ^a  

^a NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY AIST   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ETCHING; ION BOMBARDMENT; LOGIC GATES; SILICON; SUBSTRATES;

ULTRA-THIN SILICON WALL;

MOSFET DEVICES;

EID: 0036927333     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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6. M.Masahara, et al., to be published in SSDM'02.
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