Nanoscale CMOS spacer FinFET for the terabit era

IEEE Electron Device Letters

Volumn 23, Issue 1, 2002, Pages 25-27

  Choi, Yang Kyu ^b   King, Tsu Jae ^b   Hu, Chenming ^a,b  

^a IEEE

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Chemical mechanical polishing (CMP); Critical dimension (CD); Double gate; FinFET; Gate planarization; Nanoscale CMOS; Silicon on insulator (SOI); Spacer etch; Spacer lithography; Thin body; Uniformity

Indexed keywords

ANISOTROPY; CHEMICAL MECHANICAL POLISHING; CHEMICAL VAPOR DEPOSITION; CMOS INTEGRATED CIRCUITS; PHOTOLITHOGRAPHY; PLASMA ETCHING; RAPID THERMAL ANNEALING; THERMOOXIDATION;

SPACER LITHOGRAPHY;

GATES (TRANSISTOR);

EID: 0036163060     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.974801     Document Type: Article

References (9)

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5. Gate length scaling and threshold voltage control of double-gate MOSFET's
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7. Spacer FinFET: Nano-scale CMOS technology for the terabit era
8. 2
9. Characterization of surface mobility on the sidewalls of dry-etched trenches