Structural optimization of SUTBDG devices for low-power applications

IEEE Transactions on Electron Devices

Volumn 52, Issue 3, 2005, Pages 360-366

  Xiong, Shiying ^a   Bokor, Jeffrey ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Double gate (DG); Expanded source gate (S D); High ; Junction abruptness; Metal S D; Structural optimization; Weakly coupling S D

Indexed keywords

CAPACITANCE; CARRIER MOBILITY; DIELECTRIC MATERIALS; ELECTRIC CURRENTS; ELECTRIC RESISTANCE; GATES (TRANSISTOR); SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR JUNCTIONS; STRUCTURAL OPTIMIZATION;

DOUBLE GATE (DG) DEVICES; EXPANDED SOURCE/DRAIN (S/D) STRUCTURES; JUNCTION ABRUPTNESS; METAL SOURCE/DRAIN (S/D) REGIONS; WEAKLY COUPLING SOURCE/DRAIN (S/D) REGIONS;

MOSFET DEVICES;

EID: 15044346881     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.843869     Document Type: Article

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