A functional FinFET-DGCMOS SRAM cell

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2002, Pages 411-414

  Nowak, E J ^a   Rainey, B A ^a   Fried, D M ^c   Kedzierski, J ^b   Ieong, M ^b   Leipold, W ^a   Wright, J ^a   Breitwisch, M ^a  

^a IBM   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c Department of Obstetrics Gynecology   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COPPER; ELECTRIC INVERTERS; GATES (TRANSISTOR); OXIDATION; PHOTOLITHOGRAPHY; SILICON WAFERS; STATIC RANDOM ACCESS STORAGE; THRESHOLD VOLTAGE;

INTEGRATED INVERTERS;

CMOS INTEGRATED CIRCUITS;

EID: 0036923636     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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2. D.Hisamoto, et al., "A Folded channel MOSFET for Deep-sub-tenth Micron Era," IEDM 1998, pp 1032-1035.
3. X.Huang, et al., "Sub 50-nm FinFET: PFET," IEDM 1999, pp 67-70.
4. D.M.Fried, et al., "A sub-40 nm Body Thickness N-Type FinFET," 2001 Device Research Conference pp 24-25.
5. N.Lindert, et al., "Quasi planar NMOS FinFETs with sub 100 nm gate lengths," 2001 Device Research Conference pp 26-27.
6. J. Kedzierski, et al., "High-Performance symmetric-gate and CMOScompatible asymmetric-gate FinFET Device," IEDM 2001, pp 437-440.
7. B.Rainey, et al. "Demonstration of FinFET CMOS Circuits," 2002 Device Research Conference, pp 47-48.
8. S.Takagi, A.Toriumi, M.Iwase, and H.Tango, "On the Universality of Inversion Layer Mobility in Si MOSFETs: Part I-Effects of Substrate Impurity Concentration," Trans. on Elec. Devs.., V41 No12 Dec 1994, pp2357-2368.
9. W.R.Hunter, T.C.Holloway, P.K.Chatterjee, and A.F.Tasch, JR., "A New Edge-Defined Approach for Submicrometer MOSFET Fabrication," Elect.Dev.Lett., V. EDL-2 No.l, Jan 1981 pp 4-6.
10. Y.K.Choi, T.J.King, C.Hu, "Nano-scale CMOS spacer FinFET for the terabit era," Electron Device Lett. (USA) Vol.23, No.l Jan. 2002 pp 25-27.