Integrating formal verification into an advanced computer architecture course

ASEE Annual Conference Proceedings

Volumn , Issue , 2003, Pages 10753-10781

  Velev, Miroslav N ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED LOGIC DESIGN; COMPUTER HARDWARE; ENGINEERING EDUCATION; HIGH LEVEL LANGUAGES; MULTIPROCESSING PROGRAMS; PARALLEL PROCESSING SYSTEMS; PIPELINE PROCESSING SYSTEMS; PROGRAM PROCESSORS; STUDENTS; TEACHING; TECHNICAL PRESENTATIONS;

ADVANCED COMPUTER ARCHITECTURE COURSE; ALU (ARITHMETIC LOGICAL UNIT); DLX PROCESSOR; FORMAL VERIFICATION;

COMPUTER ARCHITECTURE;

EID: 8744290910     PISSN: 01901052     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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