Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 18, Issue 7, 1999, Pages 918-935

  Pandey, Manish ^a   Bryant, Randal E ^a  

^a IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATION THEORY; COMPUTER SIMULATION; DATA HANDLING; GRAPH THEORY; MATHEMATICAL MODELS; RANDOM ACCESS STORAGE; SWITCHING CIRCUITS; TRANSISTORS;

CIRCUIT STRUCTURE; FORMAL VERIFICATION; GRAPH ISOMORPHISM TESTING; STATIC RANDOM ACCESS MEMORY CIRCUITS; SYMBOLIC TRAJECTORY EVALUATION; TRANSISTOR LEVEL CIRCUITS;

INTEGRATED CIRCUIT TESTING;

EID: 0032641334     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.771176     Document Type: Article

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