Scalable hybrid verification of complex microprocessors

Proceedings - Design Automation Conference

Volumn , Issue , 2001, Pages 41-46

  Mneimneh, M ^a   Aloul, F ^a   Weaver, C ^a   Chatterjee, S ^a   Sakallah, K ^a   Austin, T ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN ALGEBRA; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; CONSTRAINT THEORY; HEURISTIC METHODS; LARGE SCALE SYSTEMS;

SCALABLE HYBRID VERIFICATION;

MICROPROCESSOR CHIPS;

EID: 0034840739     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/378239.378265     Document Type: Conference Paper

References (15)

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10. Formal verification of a pipelined microprocessor