Performance analysis and its impact on design

Computer

Volumn 31, Issue 5, 1998, Pages 41-49

  Bose, Pradip ^a,c,d,e,g   Conte, Thomas M ^b,d,f  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b NORTH CAROLINA STATE UNIVERSITY   (United States)

^c INDIAN INSTITUTE OF TECHNOLOGY   (India)

^d UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^e IEEE   (India)

^f UNIVERSITY OF DELAWARE   (United States)

^g North Carolina State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL DESIGN; COMPUTER AIDED DESIGN; COMPUTER HARDWARE; COMPUTER SIMULATION; COMPUTER SOFTWARE; MICROPROCESSOR CHIPS; PERFORMANCE;

DESIGN IMPACT; PERFORMANCE ANALYSIS;

COMPUTER AIDED ANALYSIS;

EID: 0032070245     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/2.675632     Document Type: Review

References (14)

1. J.L. Hennessey and D.A. Patterson, Computer Architecture: A Quantitative Approach, 2nd ed., Morgan Kaufmann, San Francisco, 1996.
2. T.M. Conte and C.E. Gimarc, eds., Fast Simulation of Computer Architectures, Kluwer Academic Publishers, Boston, 1995.
3. P.G. Emma, "Understanding Some Simple Processor-Performance Limits," IBM J. Research and Development, May 1997, pp. 215-232; see also P.G. Emma et al., Components of Uniprocessor Performance, Research Report RC 12203, IBM, Yorktown Heights, N.Y., Oct. 3,1986.
4. P.G. Emma, "Understanding Some Simple Processor-Performance Limits," IBM J. Research and Development, May 1997, pp. 215-232; see also P.G. Emma et al., Components of Uniprocessor Performance, Research Report RC 12203, IBM, Yorktown Heights, N.Y., Oct. 3,1986.
5. W.-H. Wang and J.-L. Baer, "Efficient Trace-Driven Simulation Methods for Cache Performance Analysis," ACM Trans. Computer Systems, Aug. 1991, pp. 222-241.
6. S. Laha, J. Patel, and R. Iyer, "Accurate Low-Cost Methods for Performance Evaluation of Cache Memory Systems," IEEE Trans. Computers, Nov. 1988, pp. 1,325-1,336.
7. R. Mattson et al., "Evaluation Techniques for Storage Hierarchies," IBM Systems J., Vol. 9, No. 2, 1970, pp. 78-117.
8. A.-T. Nguyen et al., "Accuracy and Speed-Up of Parallel Trace-Driven Architectural Simulation," Proc. Int'l Parallel Processing Symp., IEEE Computer Soc. Press, Los Alamitos, Calif., 1997, pp. 39-44.
9. W. Mangione-Smith et al., "Approaching a Machine Application Bound in Delivered Performance on Scientific Code," Proc. IEEE, 1993, pp. 1,166-1,178.
10. P. Bose, Pre-Silicon Performance Analysis and Validation, to be published by MIT Press, 1998.
11. T. Diep and J.P. Shen, "Systematic Validation of Pipeline Interlocks for Superscalar Microarchitectures," Proc. 25th. Ann. Symp. Fault-Tolerant Computing, IEEE Computer Soc. Press, Los Alamitos, Calif., pp. 163-174.
12. T.M. Conte, M.A. Hirsch, and K.N. Menezes, "Reducing State-Loss for Effective Trace Sampling of Superscalar Processors," Proc. Int'l Conf. Computer Design, IEEE Computer Soc. Press, Los Alamitos, Calif., Oct. 1996, pp. 468-477.
13. V. Iyengar, L. Trevillyan, and P. Bose, "Representative Traces for Processor Models with Infinite Cache," Proc. Second Symp. High-Performance Computer Architecture, IEEE Computer Soc. Press, Los Alamitos, Calif., Feb. 1996, pp. 62-72.
14. M. Rosenblum et al., "Using the SimOS Machine Simulator to Study Complex Computer Systems," ACM Trans. Modeling and Computer Simulation, Jan. 1997, pp. 78-103.