Automatic abstraction of memories in the formal verification of superscalar microprocessors

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2031 LNCS, Issue , 2001, Pages 252-267

  Velev, Miroslav N ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ABSTRACTING; COMPUTER CIRCUITS; SEMANTICS; MICROPROCESSOR CHIPS;

AUTOMATIC ABSTRACTIONS; BOOLEAN VARIABLES; BRANCH PREDICTION; LOGIC OF EQUALITY WITH UNINTERPRETED FUNCTIONS AND MEMORY (EUFM); MAGNITUDE REDUCTION; SUPERSCALAR MICRO-PROCESSORS; TRANSFORMATION RULES; UNINTERPRETED FUNCTIONS; POSITIVE EQUALITY;

FORMAL VERIFICATION;

EID: 84903158789     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-45319-9_18     Document Type: Conference Paper

References (22)

1. W. Ackermann, Solvable Cases of the Decision Problem, North-Holland, Amsterdam, 1954.
2. R.E. Bryant, "Symbolic Boolean Manipulation with Ordered Binary-Decision Diagrams," ACM Computing Surveys, Vol. 24, No. 3 (September 1992), pp. 293-318.
3. R.E. Bryant, S. German, and M.N. Velev, "Processor Verification Using Efficient Reductions of the Logic of Uninterpreted Functions to Prepositional Logic,"2 ACM Transactions on Computational Logic (TOCL), Vol. 2, No. 1 (January 2001).
4. R.E. Bryant, and M.N. Velev, "Boolean Satisfiability with Transitivity Constraints,"2 Computer-Aided Verification (CAV '00), E.A. Emerson and A.P. Sistla, eds., LNCS 1855, Springer-Verlag, July 2000, pp. 86-98.
5. R.E. Bryant, and M.N. Velev, "Boolean Satisfiability with Transitivity Constraints,"2 Tech- nical Report CMU-CS-00-101, Carnegie Mellon University, 2000.
6. J.R. Burch, and D.L. Dill, "Automated Verification of Pipelined Microprocessor Control," Computer-Aided Verification (CAV '94), D.L. Dill, ed., LNCS 818, Springer-Verlag, June 1994, pp. 68-80. http://sprout.Stanford. edu/papers.html.
7. J.R. Burch, "Techniques for Verifying Superscalar Microprocessors," 33rd Design Automation Conference (DAC '96), June 1996, pp. 552-557.
8. CUDD-2.3.0, http://vlsi.Colorado.edu/~fabio.
9. A. Goel, K. Sajid, H. Zhou, A. Aziz, and V Singhal, "BDD Based Procedures for a Theory of Equality with Uninterpreted Functions," Computer-Aided Verification (CAV '98), A.J. Hu and M.Y. Vardi, eds., LNCS 1427, Springer-Verlag, June 1998, pp. 244-255.
10. J.L. Hennessy, and D.A. Patterson, Computer Architecture: A Quantitative Approach, 2nd edition, Morgan Kaufmann Publishers, San Francisco, CA, 1996.
11. R. Hosabettu, "Systematic Verification of Pipelined Microprocessors," Ph.D. thesis, Department of Computer Science, University of Utah, August 2000. http://www.cs.utah.edu/~hosabett.
12. S. Malik, A.R. Wang, R.K. Brayton, and A. Sangiovani-Vincentelli, "Logic Verification Using Binary Decision Diagrams in a Logic Synthesis Environment," International Conference on Computer-Aided Design (ICCAD '88), November 1988, pp. 6-9.
13. G. Ritter, H. Eveking, and H. Hinrichsen, "Formal Verification of Designs with Complex Control by Symbolic Simulation," Correct Hardware Design and Verification Methods (CHARME '99), L. Pierre and T. Kropf, eds., LNCS 1703, Springer-Verlag, September 1999, pp. 234-249.
14. R. Rudell, "Dynamic Variable Ordering for Ordered Binary Decision Diagrams," International Conference on Computer-Aided Design (ICCAD'93), November 1993, pp. 42-47.
15. M.N. Velev, and R.E. Bryant, "Exploiting Positive Equality and Partial Non-Consistency in the Formal Verification of Pipelined Microprocessors,"2 36th Design Automation Conference (DAC '99), June 1999, pp. 397-401.
16. M.N. Velev, and R.E. Bryant, "Superscalar Processor Verification Using Efficient Reductions of the Logic of Equality with Uninterpreted Functions to Prepositional Logic,"2 Correct Hardware Design and Verification Methods (CHARME '99), L. Pierre and T. Kropf, eds., LNCS 1703, Springer-Verlag, September 1999, pp. 37-53.
17. M.N. Velev, and R.E. Bryant, "Formal Verification of Superscalar Microprocessors with Multicycle Functional Units, Exceptions, and Branch Prediction,"2 37th Design Automation Conference (DAC '00), June 2000, pp. 112-117.
18. M.N. Velev, and R.E. Bryant, "Formal Verification of Superscalar Microprocessors with Multicycle Functional Units, Exceptions, and Branch Prediction,"2 Technical Report CMU-CS-00-116, Carnegie Mellon University, 2000.
19. M.N. Velev, "Formal Verification of VLIW Microprocessors with Speculative Execution,"2 Computer-Aided Verification (CAV '00), E.A. Emerson and A.P. Sistla, eds., LNCS 1855, Springer-Verlag, July 2000, pp. 296-311.
20. M.N. Velev, and R.E. Bryant, "Effective Use of Boolean Satisfiability Procedures in the Formal Verification of Superscalar and VLIW Microprocessors,"2 submitted for publication, 2000.
21. M.N. Velev, and R.E. Bryant, "EVC: A Validity Checker for the Logic of Equality with Uninterpreted Functions and Memories, Exploiting Positive Equality and Conservative Transformations,"2 submitted for publication, 2001.
22. P.J. Windley, and J.R. Burch, "Mechanically Checking a Lemma Used in an Automatic Verification Tool," Formal Methods in Computer-Aided Design (FMCAD '96), M. Srivas and A. Camilleri, eds., LNCS 1166, Springer-Verlag, November 1996, pp. 362-376.