Automatic verification of in-order execution in microprocessors with fragmented pipelines and multicycle functional units

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2002, Pages 36-43

  Mishra, Prabhat ^a   Tomiyama, Hiroyuki ^a   Dutt, Nikil ^a   Nicolau, Alex ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURE DESCRIPTION LANGUAGES; AUTOMATIC VERIFICATION; MODELING TECHNIQUE; PERFORMANCE REQUIREMENTS; PIPELINED PROCESSOR; PROCESSOR PIPELINES; SYSTEM ARCHITECTS; TOP-DOWN APPROACH;

ARCHITECTURE; EXHIBITIONS; PIPELINES;

PIPELINE PROCESSING SYSTEMS;

EID: 0348120352     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2002.998247     Document Type: Conference Paper

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