An integrated laboratory for computer architecture and networking

Proceedings of the 2002 Workshop on Computer Architecture Education, WCAE 2002 - Held in conjunction with the 29th International Symposium on Computer Architecture

Volumn , Issue , 2002, Pages

  Tateoka, Takamichi ^a   Suzuki, Mitsugu ^a   Kono, Kenji ^a   Maeda, Youichi ^a   Abe, Kôki ^a  

^a UNIVERSITY OF ELECTRO COMMUNICATIONS   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CURRICULA; EDUCATION; ENGINEERING EDUCATION; LABORATORIES; NETWORK ARCHITECTURE; PROGRAM COMPILERS; STUDENTS;

COMPUTER SCIENCE CURRICULA; DESIGN AND DEVELOPMENT; LARGE SYSTEM; NETWORKING PROTOCOLS; OBJECT CODE;

COMPUTER ARCHITECTURE;

EID: 84969219564     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1275462.1275490     Document Type: Conference Paper

References (8)

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3. T. Katsu, D. Oosuga, M. Tsuruta, and K. Abe. Design and implementation of a 32 bit RISC processor MinIPS. Bull. of the Univ. of Electro-Comm., 10(2):71-78, 1997.
4. K. Morita and K. Abe. Implementation of UDP/IP protocol stack on FPGA and its performance evaluation. In Proc. IPSJ General Conf. Special5, pages 157-158.
5. The Joint Task Force on Computing Curricula IEEE-CS and ACM. Computing Curricula - Final Draft. http://www.computer.org/education/cc2001/final/index.htm, December 2001.
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8. T. Watanabe. Composing a compiler. Asakura Pub., 1998.