Calibration of microprocessor performance models

Computer

Volumn 31, Issue 5, 1998, Pages 59-65

  Black, Bryan ^a,b   Shen, John Paul ^a,c,d,e  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b Elec and Comp Eng Department ^*

^c UNIVERSITY OF MICHIGAN   (United States)

^d UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^e CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CALIBRATION; COMPUTATIONAL COMPLEXITY; MICROPROCESSOR CHIPS; PERFORMANCE;

MICROPROCESSOR PERFORMANCE MODELS; VALIDATION;

COMPUTER SIMULATION;

EID: 0032069891     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/2.675637     Document Type: Review

References (10)

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2. A. Huang and T. Diep, MW Developer's Guide, Tech. Report CMuART-95-1, Carnegie Mellon Univ., Pittsburgh, Aug. 1995.
3. T. Diep and J.P. Shen, "VMW: A Visualization-Based Microarchitecture Workbench," Computer, Dec. 1995, pp. 57-64.
4. B. Black et al., "Can Trace-Driven Simulation Accurately Predict Superscalar Performance?" Proc. IEEE Int'l Conf. Computer Design, IEEE Computer Soc. Press, Los Alamitos, Calif., pp. 478-485.
5. K. Diefendorff and E. Silha, "The PowerPC User Instruction Set Architecture," IEEE Micro, Oct. 1994, pp. 30-41.
6. S.P. Song, M. Denman, and J. Chang, "The PowerPC 604 RISC Microprocessor," IEEE Micro, Oct. 1994, pp. 8-17.
7. PowerPC 604 RISC Microprocessor User's Manual, IBM Microelectronics Division, 1994.
8. M. Lipasti, C. Wilkerson, and J.P. Shen, "Value Locality and Data Speculation," Proc. 7th Int'l Conf. Architectural Support for Programming Languages and Operating Systems, Computer Soc. Press, Los Alamitos, Calif., pp. 138-147.
9. S. McFarling, Combining Branch Predictors, Tech. Note TN-36, Western Research Lab, Digital Equipment Corp., June 1993.
10. E. Rotenberg, S. Bennett, and J. Smith, "Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching," Proc. 29th Int'l Symp. Microarchitecture, Dec. 1996, pp. 24-34.