Experience with term level modeling and verification of the M∗CORE™ microprocessor core

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Volumn 2001-January, Issue , 2001, Pages 109-114

  Lahiri, S ^a   Pixley, C ^b   Albin, K ^c  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b SYNOPSYS INC   (United States)

^c MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN; MICROPROCESSOR CHIPS;

AUTOMATED VERIFICATION; DECISION PROCEDURE; DESIGN EXPLORATION; INSTRUCTION PREFETCHING; MICRO ARCHITECTURES; MICROPROCESSOR CORE; MICROPROCESSOR DESIGNS; UNINTERPRETED FUNCTIONS;

INTEGRATED CIRCUIT DESIGN;

EID: 84952793183     PISSN: 15526674     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HLDVT.2001.972816     Document Type: Conference Paper

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