Nuts and bolts of core and SoC verification

Proceedings - Design Automation Conference

Volumn , Issue , 2001, Pages 249-252

  Albin, K ^a  

^a MOTOROLA INC   (United States)

Author keywords

Biased random simulation; Monitors; Testbenches; Verification

Indexed keywords

ABILITY TESTING; COMPUTER AIDED DESIGN; HTML; INTEGRATED CIRCUIT LAYOUT; INTERFACES (COMPUTER); MICROPROCESSOR CHIPS;

DATA MANAGEMENT;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0034853725     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/378239.378475     Document Type: Conference Paper

References (10)

1. Design constraints in symbolic model checking
2. Automatic Vector Generaion Using Constraints and Biasing
3. Integrating model checking into the semiconductor design flow
4. Integrated formal and informal design verification of commercial integrated circuits
5. Automatic verification of pipelined microprocessor control
6. Exploiting positive equality in a logic of equality with uninterpreted functions
7. ACL2 theorems about commercial microprocessors
8. A methodology for large-scale hardware verification