Practical formal verification in microprocessor design

IEEE Design and Test of Computers

Volumn 18, Issue 4, 2001, Pages 16-25

  Jones, Robert B ^a   O'Leary, John W ^a   Seger, Carl Johan H ^a   Aagaard, Mark D ^b   Melham, Thomas F ^c  

^a INTEL CORPORATION   (United States)

^b UNIVERSITY OF WATERLOO   (Canada)

^c UNIVERSITY OF GLASGOW   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

FORMAL VERIFICATION;

ADDERS; ALGORITHMS; COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER GRAPHICS; COMPUTER PROGRAMMING LANGUAGES; GRAPHICAL USER INTERFACES; MICROPROCESSOR CHIPS; THEOREM PROVING;

INTEGRATED CIRCUIT LAYOUT;

EID: 0035394259     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.936245     Document Type: Article

References (10)

1. Formal verification by symbolic evaluation of partially-ordered trajectories
2. A methodology for large-scale hardware verification
3. Graph-based algorithms for Boolean function manipulation
4. Formally verifying IEEE compliance of floating-point hardware
5. Formal verification using parametric representations of Boolean constraints
6. Combining theorem proving and trajectory evaluation in an industrial environment
7. Integrating model checking into the semiconductor design flow