Formal verification of an ARM processor

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1999, Pages 282-287

  Patankar, Vishnu A ^a   Jain, Alok ^a   Bryant, Randal E ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

PARALLEL PROCESSING SYSTEMS; PIPELINE PROCESSING SYSTEMS;

FORMAL VERIFICATION METHODOLOGY; SYMBOLIC TRAJECTORY EVALUATION;

FORMAL LOGIC;

EID: 0032713341     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/icvd.1999.745161     Document Type: Conference Paper

References (11)