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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 12, 2001, Pages 1443-1454

An efficient graph representation for arithmetic circuit verification

(2) Chen, Yirng An a,b Bryant, Randal E a,c

a IEEE (United States)

b Novas Software Inc (United States)

c Carnegie Mellon University ^* (United States)

Author keywords

*PHDD; BDD; Binary moment diagram; BMD; Formal verification; HDD; Hybrid decision diagram; Multiplicative power hybrid decision diagram

Indexed keywords

BINARY MOMENT DIAGRAMS; MULTIPLICATIVE POWER HYBRID DECISION DIAGRAMS;

BOOLEAN ALGEBRA; COMPUTATIONAL COMPLEXITY; DATA STRUCTURES; DECISION THEORY; ENCODING (SYMBOLS); GRAPHIC METHODS; MULTIPLYING CIRCUITS; VECTORS;

DIGITAL ARITHMETIC;

EID: 0035670976 PISSN: 02780070 EISSN: None Source Type: Journal
DOI: 10.1109/43.969437 Document Type: Article

Times cited : (11)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.