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Volumn , Issue , 1998, Pages 638-643

Functional verif icat ion of a mu it i ple-issue, out-of-order, superscalar alpha processor- The dec alpha 21264 microprocessor

Author keywords

Alpha; Architecture; Coverage analysis 21264; Microprocessor; Pseudo random; Validation; Verification

Indexed keywords

ARCHITECTURE; DESIGN; MICROPROCESSOR CHIPS; VERIFICATION; BUFFER STORAGE; COMPUTER SIMULATION; RANDOM PROCESSES; RESPONSE TIME (COMPUTER SYSTEMS); TIMING CIRCUITS;

EID: 0031639694     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (60)

References (6)
  • 1
    • 0002327718 scopus 로고    scopus 로고
    • Digital 21264 sets new standard
    • (October 28)
    • Linley Gwennap, "Digital 21264 Sets New Standard, " Microprocessor Report (October 28, 1996): 11-16.
    • (1996) Microprocessor Report , pp. 11-16
    • Gwennap, L.1
  • 2
    • 0029221753 scopus 로고
    • Functional verification of a multiple-issue, pipelined, superscalar alpha processor-the alpha 21164 CPU chip
    • Mike Kantrowitz and Lisa Noack, "Functional Verification of a Multiple-issue, Pipelined, Superscalar Alpha Processor-the Alpha 21164 CPU Chip, " Digital Technical Journal, vol. 7, no. 1 (1995): 136-143.
    • (1995) Digital Technical Journal , vol.7 , Issue.1 , pp. 136-143
    • Kantrowitz, M.1    Noack, L.2
  • 3
    • 0342883218 scopus 로고
    • Logical verification of the NVAX CPU chip design
    • (Summer)
    • W. Anderson, "Logical Verification of the NVAX CPU Chip Design, " Digital Technical Journal, vol. 4, no. 3 (Summer 1992): 38-46.
    • (1992) Digital Technical Journal , vol.4 , Issue.3 , pp. 38-46
    • Anderson, W.1
  • 4
    • 0001314320 scopus 로고
    • Verification of the IBM RISC system/6000 by a dynamic biased pseudo-random test program generator
    • A. Aharon, A. Bar-David, B. Dorfman, E. Gofman, M. Leibowitz, and V. Schwartzburd, "Verification of the IBM RISC System/6000 by a Dynamic Biased Pseudo-random Test Program Generator, " IBM Systems Journal, vol. 30, no. 4 (1991):527-538.
    • (1991) IBM Systems Journal , vol.30 , Issue.4 , pp. 527-538
    • Aharon, A.1    Bar-David, A.2    Dorfman, B.3    Gofman, E.4    Leibowitz, M.5    Schwartzburd, V.6
  • 6
    • 0025470393 scopus 로고
    • Verifying a multiprocessor cache controller using random test generation
    • (August)
    • D. Wood, G. Gibson, and R. Katz, "Verifying a Multiprocessor Cache Controller Using Random Test Generation, " IEEE Design and Test of Computers (August 1990): 13-25.
    • (1990) IEEE Design and Test of Computers , pp. 13-25
    • Wood, D.1    Gibson, G.2    Katz, R.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.