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Volumn , Issue , 1998, Pages 638-643
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Functional verif icat ion of a mu it i ple-issue, out-of-order, superscalar alpha processor- The dec alpha 21264 microprocessor
a a a a a a a |
Author keywords
Alpha; Architecture; Coverage analysis 21264; Microprocessor; Pseudo random; Validation; Verification
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Indexed keywords
ARCHITECTURE;
DESIGN;
MICROPROCESSOR CHIPS;
VERIFICATION;
BUFFER STORAGE;
COMPUTER SIMULATION;
RANDOM PROCESSES;
RESPONSE TIME (COMPUTER SYSTEMS);
TIMING CIRCUITS;
ALPHA;
COVERAGE ANALYSIS;
FUNCTIONAL COVERAGE;
FUNCTIONAL VERIFICATION;
INSTRUCTIONS PER CYCLES;
MULTIPLE OPERATING SYSTEMS;
PSEUDO RANDOM;
VALIDATION;
AUTOMATION;
COMPUTER AIDED NETWORK ANALYSIS;
FUNCTIONAL VERIFICATION;
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EID: 0031639694
PISSN: 0738100X
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (60)
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References (6)
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