Formal verification of superscalar microprocessors with multicycle functional units, exceptions, and branch prediction

Proceedings - Design Automation Conference

Volumn , Issue , 2000, Pages 112-117

  Velev, Miroslav N ^a   Bryant, Randal E ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; COMPUTER SIMULATION; COMPUTER SOFTWARE; DATA STRUCTURES; FINITE AUTOMATA; GRAPH THEORY; LOGIC DESIGN; MICROCOMPUTERS;

FORMAL VERIFICATION; POSITIVE EQUALITY WITH UNINTERPRETED FUNCTIONS; SUPERSCALAR MICROPROCESSORS;

INTEGRATED CIRCUIT TESTING;

EID: 0033684177     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (22)