Techniques for verifying superscalar microprocessors

Proceedings - Design Automation Conference

Volumn , Issue , 1996, Pages 552-557

  Burch, Jerry R ^a  

^a CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; COMPUTER ARCHITECTURE; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; LOGIC DESIGN; MICROPROCESSOR CHIPS; POLYNOMIALS;

DLX ARCHITECTURE; INSTRUCTION SET ARCHITECTURE; SUPERSCALAR MICROPROCESSORS;

PIPELINE PROCESSING SYSTEMS;

EID: 0029724075     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/240518.240623     Document Type: Conference Paper

References (13)