Validation of pipelined processor designs using esterel tools: A case study

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1633, Issue , 1999, Pages 84-95

  Ramesh, S ^a   Bhaduri, Purandar ^b  

^a INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

^b Tata Infotech Limited   (India)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED ANALYSIS; ESTERS; FORMAL VERIFICATION; INTEGRATED CIRCUIT DESIGN; PIPELINES; PROGRAM DEBUGGING;

HIGH LEVEL DESCRIPTION; MODERN PROCESSORS; OUT-OF-ORDER EXECUTION; PIPELINE CONTROLS; PIPELINED PROCESSOR; PROCESSOR DESIGN; SPEED-UP TECHNIQUES; VERIFICATION TOOLS;

PIPELINE PROCESSING SYSTEMS;

EID: 84957063926     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-48683-6_10     Document Type: Conference Paper

References (11)

1. S. Berezin, A. Biere, E. Clarke, and Y. Zhu. Combining symbolic model checking with uninterpreted functions for out of order processor verification. In G. Gopalakrishnan and P. Windley, editors, FMCAD'98, LNCS 1522. Springer Verlag, 1998.
2. G. Berry. The Foundations of Esterel. In G. Plotkin, C. Stirling, and M. Tofte, editors, Proof, Language and Interaction: Essays in Honour of Robin Milner. MIT Press, 1998.
3. G. Berry and G. Gonthier. The Esterel synchronous programming language: Design, semantics, implementation. Science Of Computer Programming, 19(2), 1992.
4. A. Bouali. XEVE: An Esterel Verification Environment. Available by ftp from ftp-sop.inria.fr as file /meije/verif/xeve-doc.ps.gz.
5. A. Bouali, A. Ressouche, R. de Simone, and V. Roy. The FcTools User Manual. Available by ftp from ftp-sop.inria.fr as file /meije/verif/fc2userman.ps.
6. R. E. Bryant. Formal Verification of Pipelined Processors. In Proc. TACAS 98, LNCS 1384. Springer Verlag, March-April 1998.
7. J. R. Burch and D. L. Dill. Automatic Verification of Pipelined Microprocessor Control. In Proc. CAV'94, LNCS 818. Springer Verlag, June 1994.
8. J. Hennessy and D. Patterson. Computer Architecture: A Quantitative Approach, Second Edition. Morgan Kaufman Publishers Inc., 1995.
9. R. Hosabettu, M. Srivas, and G. Gopalakrishnan. Decomposing the Proof of Correctness of Pipelined Microprocessors. In Proc. CAV'98, LNCS 1427. Springer Verlag, June/July 1998.
10. T. Kropf, editor. Formal Hardware Verification, LNCS 1287. Springer Verlag, 1997.
11. J. U. Skakkebaek, R. B. Jones, and D. L. Dill. Formal Verification of Out-of-order Execution using Incremental Flushing. In Proc. CAV'98, LNCS 1427. Springer Verlag, June 1998.