Core-based system-on-chip testing: Challenges and opportunities

Journal of the Chinese Institute of Electrical Engineering, Transactions of the Chinese Institute of Engineers, Series E/Chung KuoTien Chi Kung Chieng Hsueh K'an

Volumn 8, Issue 4, 2001, Pages 335-353

  Wu, C W ^a   Li, J F ^a   Huang, C T ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

Built in self test (BIST); Core test language; IC testing; IEEE P1500 standard; System on chip (SOC); Test scheduling

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; BUILT-IN SELF TEST; DATA REDUCTION; DESIGN FOR TESTABILITY; RANDOM ACCESS STORAGE; SEMICONDUCTOR DEVICE MANUFACTURE; STANDARDS; VLSI CIRCUITS;

CORE TEST LANGUAGE; CORE TEST PLUG-AND-PLAY; DEEP-SUBMICRON TECHNOLOGY; SYSTEM-ON-CHIP TESTING; TEST WRAPPER; USER-DEFINED LOGIC;

SEMICONDUCTOR DEVICE TESTING;

EID: 0035506005     PISSN: 10234462     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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