System-on-a-chip test-data compression and decompression architectures based on Golomb codes

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 3, 2001, Pages 355-368

  Chandra, Anshuman ^a,b   Chakrabarty, Krishnendu ^a,b  

^a IEEE   (United States)

^b Duke University   (United States)

Author keywords

Automatic test equipment (ATE); Decompression architecture; Difference vector; Embedded core testing; Precomputed test sets; Test set encoding; Testing time; Variable to variable length codes

Indexed keywords

AUTOMATIC TEST EQUIPMENT; GOLOMB CODES; INTERLEAVING DECOMPRESSION ARCHITECTURE; SYSTEM-ON-A-CHIP; VARIABLE-TO-VARIABLE LENGTH CODES;

AUTOMATIC TESTING; BUILT-IN SELF TEST; CODES (SYMBOLS); DIFFERENTIATION (CALCULUS); INTEGRATED CIRCUIT TESTING; MICROPROCESSOR CHIPS; THEOREM PROVING;

DATA COMPRESSION;

EID: 0035271735     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.913754     Document Type: Article

References (25)

1. Testing embedded-core based system chips
2. Logic BIST for large industrial designs
3. Testing ICs: Getting to the core of the problem
4. Efficient BIST TPG design and test set compaction via input reduction
5. Design of built-in test generator circuits using width compression
6. Built-in pattern generation for high-performance circuits using twisted-ring counters
7. Built-in self testing of sequential circuits using precomputed test sets
8. Deterministic built-in pattern generation for sequential circuits
9. Scan vector compression/decompression using statistical coding
10. Test vector decompression via cyclical scan chains and its application to testing core-based design
11. Test set compaction algorithms for combinational circuits
12. On compacting test sets by addition and removal of vectors
13. An efficient method for compressing test data
14. COMPACT: A hybrid method for compressing test data
15. Run-length encoding
16. Image data compression by predictive coding, part I: Prediction algorithm
17. On adaptive strategies for an extended family of Golomb-type code
18. Optimal prefix codes for two-sided geometric distribution
19. Test requirements for embedded core-based systems and IEEE P1500
20. Research in VLSI circuit testing, verification, and diagnosis
21. SIS: A system for sequential circuit synthesis
22. On the generation of test patterns for combinational circuits
23. High-performance circuit testing using slow-speed testers
24. High-speed serialiazing/de-serializing design-for-test methods for evaluating a 1 GHz microprocessor