Testing embedded-core-based system chips

Computer

Volumn 32, Issue 6, 1999, Pages 52-60

  Zorian, Yervant ^a,d   Marinissen, Erik Jan ^b   Sujit, Dey ^c  

^a Logic Visions Inc   (United States)

^b PHILIPS RESEARCH LABORATORIES   (Netherlands)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d LogicVision Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; COMPUTER HARDWARE DESCRIPTION LANGUAGES; DATA STORAGE EQUIPMENT; DIGITAL INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; LINEAR INTEGRATED CIRCUITS; PRINTED CIRCUIT BOARDS; PROGRAM DEBUGGING; QUALITY ASSURANCE; SOFTWARE PROTOTYPING;

AUTOMATIC TEST EQUIPMENT; SYSTEM ON CHIP; TEST ACCESS MECHANISM; USER DEFINED LOGIC;

MICROPROCESSOR CHIPS;

EID: 0032667182     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/2.769444     Document Type: Article

References (12)

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9. Y. Zorian, E.J. Marinissen, and S. Dey, "Testing Embedded-Core-Based System Chips," Proc. IEEE Int'l Test Conf., IEEE CS Press, Los Alamitos, Calif., 1998, pp. 130-143.
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11. E.J. Marinissen et al., "A Structured and Scalable Mechanism for Test Access to Embedded Reusable Cores," Proc. IEEE Int'l Test Conf., IEEE CS Press, Los Alamitos, Calif., 1998, pp. 284-293.
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