Simulation-based test algorithm generation for random access memories

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2000, Pages 291-296

  Wu, Chi Feng ^a   Huang, Chih Tsun ^a   Cheng, Kuo Liang ^a   Wu, Cheng Wen ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; ELECTRONICS INDUSTRY; FAILURE ANALYSIS; MATHEMATICAL MODELS; OPTIMIZATION; RANDOM ACCESS STORAGE;

ADDRESS DECODER FAULT; FAULT MODEL; STUCK OPEN FAULT; TEST ALGORITHM GENERATION BY SIMULATION; TRANSITION FAULT;

INTEGRATED CIRCUIT TESTING;

EID: 0033749132     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (16)