Addressable test ports an approach to testing embedded cores

IEEE International Test Conference (TC)

Volumn , Issue , 1999, Pages 1055-1064

  Whetsel, Lee ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDRESSABLE TEST PORTS; INTEGRATED CIRCUIT ARCHITECTURE; INTELLECTUAL PROPERTY CORES;

ASSOCIATIVE STORAGE; COMPUTATIONAL COMPLEXITY; DIGITAL INTEGRATED CIRCUITS; EMBEDDED SYSTEMS; INTELLECTUAL PROPERTY; INTERFACES (COMPUTER); MIXER CIRCUITS; SEMICONDUCTING SILICON;

DESIGN FOR TESTABILITY;

EID: 0033346855     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)