An integrated system-on-chip test framework

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2001, Pages 138-144

  Larsson, Erik ^a   Peng, Zebo ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED DESIGN ENVIRONMENTS; INTEGRATED SYSTEM-ON-CHIP; PARALLELIZATIONS; RESOURCE PLACEMENT; SYSTEM-ON-CHIP; TEST ACCESS MECHANISM; TEST APPLICATION TIME; TEST SCHEDULING;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; EXHIBITIONS; INTEGRATED CIRCUIT TESTING; MACHINE DESIGN; PROGRAMMABLE LOGIC CONTROLLERS;

TESTING;

EID: 84893651091     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2001.915014     Document Type: Conference Paper

References (12)

1. A. Benso, S. Cataldo, S. Chiusano, P. Prinetto, Y. Zorian, A High-Level EDA Environment for the Automatic Insertion of HD-BIST Structures, JETTA, Vol. 16. 3, pp 179-184, June 2000.
2. Y. Zorian, A distributed BIST control scheme for complex VLSI devices, Proc. of VLSI Test Symp., pp. 4-9, April 1993.
3. M. Garg, A. Basu, T. C. Wilson, D. K. Banerji, J. C. Majithia, A New Test Scheduling Algorithm for VLSI Systems, Proc. of the Symp. on VLSI Design, pp. 148-153, November 1999.
4. K. Chakrabarty, Test Scheduling for Core-Based Systems, Proc. of Int. Conf on CAD, pp. 391-394, January 1991.
5. R. Chou, K. Saluja, V. Agrawal, Scheduling Tests for VLSI Systems Under Power Constraints, IEEE Trans, on VLSI Systems, Vol. 5, No. 2, pp. 175-185, June 1997.
6. V. Muresan et al, A Comparison of Classical Scheduling Approaches in Power-Constrained Block-Test Scheduling, Proc. of Int. Test Conf, pp. 882-891, 3-5 October 2000.
7. H. Bleeker et al., Boundary-Scan Test: A Practical Approach, Kluwer Academic Publishers, ISBN 0-7923-9296-5, 1993.
8. E. J. Marinissen et al., A Structured and Scalable Mechanism for Test Access to Embedded Reusable Cores, Proc. of International Test Conf., pp 284-293, October 18-23, 1998.
9. IEEE P1500 Web site. http://grouper.ieee.org/grpups/1500/.
10. M. Sugihara, H. Date, H. Yasuura, A Test Methodology for Core-Based System LSIs, IEICE Trans, on Fund. vol. E81- A, No. 12, pp. 2640-2645, December 1998.
11. J. Aerts, E. J. Marinissen, Scan Chain Design for Test Time Reduction in Core-Based ICs, Proceedings of the International Test Conference, pp 448-457, 1998.
12. G. Hetherington et al., Logic BIST for Large Industrial Designs: Real Issues and Case Studies, Proceedings of the International Test Conference, pp. 358-367, 1999.