Scheduling tests for VLSI systems under power constraints

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 5, Issue 2, 1997, Pages 175-185

  Chou, Richard M ^a   Saluja, Kewal K ^a,c   Agrawal, Vishwani D ^b,c  

^a University of Wisconsin Madison   (United States)

^b LUCENT TECHNOLOGIES   (United States)

^c IEEE

Author keywords

Built in self test (BIST); Low power testing; Power constrained scheduling; Test scheduling; VLSI testing

Indexed keywords

ALGORITHMS; GRAPH THEORY; INTEGRATED CIRCUIT TESTING; SCHEDULING;

BUILT IN SELF TEST (BIST); POWER RATINGS; RESOURCE GRAPH FORMULATION;

VLSI CIRCUITS;

EID: 0031163752     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.585217     Document Type: Article

References (23)

1. M. Abadir and M. A. Breuer, "Constructing optimal test schedules for VLSI circuits having built-in test hardware," in Proc. Int. Symp. Fault-Tolerant Comp., June 1985, pp. 165-170.
2. R. Batni, J. Russell, and C. R. Kime, "An efficient algorithm for finding an irredundant set cover," J. ACM, vol. 21, no. 3, pp. 351-355, July 1974.
3. L. Benini, M. Favalli, P. Olivo, and B. Riccò, "A novel approach to cost-effective estimate of power dissipationin CMOS ICs," in Proc. European Conf. Design Automation, Feb. 1993, pp. 354-360.
4. R. M. Chou, K. K. Saluja, and V. D. Agrawal, "Power constraint scheduling of tests," in Proc. 7th Int. Conf. VLSI Design, Jan. 1994, pp. 271-274.
5. C. Craig, C. R. Kime, and K. K. Saluja, "Test scheduling and control for VLSI built-in self-test," IEEE Trans. Comput., vol. 37, pp. 1099-1109, Sept. 1988.
6. S. Devadas, K. Keutzer, and J. White, "Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation," IEEE Trans. Computer-Aided Design, vol. 11, pp. 373-383, Mar. 1992.
7. D. L. Dietmeyer, Logic Design of Digital Systems, 2nd ed. Boston, MA: Allyn and Bacon, 1979.
8. F. Dresig, P. Lanchès, O. Rettig, and U. Baitinger, "Simulation and reduction of cmos power dissipation at logic level," in Proc. European Conf. Design Automation, Feb. 1993, pp. 341-346.
9. M. Gonzales, "Deterministic processor scheduling," ACM Comput. Surv., vol. 9, no. 3, pp. 173-204, Sept. 1977.
10. F. Harary, Graph Theory. Reading, MA: Addison-Wesley, 1969.
11. N. Jarwala, C. Yau, P. Stiling, and E. Tammaru, "A framework for boundary-scan based system test and diagnosis," in Proc. Int. Test Conf., Sept. 1992, pp. 993-998.
12. W. B. Jone, C. Papachristou, and M. Pereira, "A scheme for overlaying concurrent testing of VLSI circuits," in Proc. Design Automation Conf., June 1989, pp. 531-536.
13. C. R. Kime and K. K. Saluja, "Test scheduling in testable VLSI circuits," in Proc. Int. Symp. Fault-Tolerant Comput., June 1982, pp. 406-412.
14. Z. Kohavi, Switching and Finite Automata Theory, 2nd ed. New York: McGraw-Hill, 1978.
15. A. Krasniewski and A. Albicki, "Automatic design of exhaustively self-testing chips with BILBO modules," in Proc. Int. Test Conf., Nov. 1985, pp. 362-371.
16. E. J. McCluskey, Introduction to the Theory of Switching Circuits. New York: McGraw-Hill, 1965.
17. J. P. Roth, "Computer solutions to minimum cover problems," Operations Research, vol. 17, no. 3, pp. 455-465, May/June 1969.
18. K. K. Saluja, C. R. Kime, and C. Craig, "Design of control for scheduling tests in testable VLSI circuits," Dep. Elec. Comput. Eng., Univ. Newcastle, New South Wales, Australia, Tech. Rep. EE8540, Sept. 1985.
19. A. Shneider, "Classification analysis of heuristic algorithms for graph coloring," Cybernet., vol. 20, pp. 484-492, July/Aug. 1984.
20. M. N. Swamy and K. Thulasiraman, Graphs, Networks, and Algorithms. New York: Wiley, 1981.
21. R. E. Tulloss and C. Yau, "BIST and boundary-scan for board level test: Test program pseudocode," in Proc. European Test Conf., Apr. 1989, pp. 106-111.
22. P. Vanoostende, P. Six, and H. De Man, "Priti: Estimation of maximal currents and current derivatives in complex cmos circuits using activity waveforms," in Proc. European Conf. Design Automation, Feb. 1993, pp. 347-353.
23. Y. Zorian, "A distributed BIST control scheme for complex VLSI devices," in Proc. 11th IEEE VLSI Test Symp., Apr. 1993, pp. 4-9.