CAS-BUS: A scalable and reconfigurable test access mechanism for systems on a chip

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2000, Pages 141-145

  Benabdenebi, Mounir ^a   Maroufi, Walid ^a   Marzouki, Meryem ^a  

^a UNIVERSITÉ PIERRE ET MARIE CURIE   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ACCESS SWITCHES; RECONFIGURABILITY; RECONFIGURABLE; SYSTEMS-ON-A CHIPS; TEST ACCESS MECHANISM;

EXHIBITIONS;

BUSES;

EID: 84893636657     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2000.840030     Document Type: Conference Paper

References (8)

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3. P. Harrod. Testing reusable ip - a case study. In International Test Conference, pages 493-498, Atlantic city, NJ, September 1999.
4. E. J. Marinissen and al. A structured and scalablemechanismfor test access to embedded reusable cores. In International Test Conference, Washington, DC, October 1998.
5. P. Varma and S. Bhatia. A structured test re-use methodology for core-based system chips. In International Test Conference, Washington, DC, October 1998.
6. R. K. Gupta and Y. Zorian. Introducing core-based system design. IEEE Design and Test of Computers, pages 15-25, October 1997.
7. Y. Zorian, E. J. Marinissen, and S. Dey. Testing embedded-core based system chips. In International Test Conference, Washington D. C., USA, 1998.
8. Y. Zorian. Testing the monster chip. IEEE Spectrum, pages 54-60, July 1999.