BRAINS: A BIST compiler for embedded memories

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2000, Pages 299-307

  Cheng, Chuang ^a   Huang, Chih Tsun ^a   Huang, Jing Reng ^a   Wu, Cheng Wen ^a   Wey, Chen Jong ^b   Tsai, Ming Chang ^b  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b Global Unichip   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DESIGN FOR TESTABILITY; DIGITAL CIRCUITS; EMBEDDED SYSTEMS; PROGRAM COMPILERS; STORAGE ALLOCATION (COMPUTER); BUILT-IN SELF TEST; INTEGRATED CIRCUIT DESIGN; MEMORY ARCHITECTURE; STATIC RANDOM ACCESS STORAGE;

BIST FOR RAM IN SECONDS (BRAIN); SYSTEM ON CHIP (SOC); VERILOG;

BUILT-IN SELF TEST; DYNAMIC RANDOM ACCESS STORAGE;

BUILD IN SELF TESTS; BUILT-IN SELF-TEST CIRCUITS; BUILTIN SELF TESTS (BIST); EMBEDDED MEMORY; MEMORY SPECIFICATION; MEMORY TESTS; SPECIFICATION REQUIREMENT; TEST CODE; TEST REQUIREMENTS; TEST-BENCH;

EID: 0034513723     PISSN: 10636722     EISSN: None     Source Type: Journal    
DOI: 10.1109/DFTVS.2000.887170     Document Type: Article

References (14)

1. K. K. Saluja S. H. Sng K. Kinoshita Built-in self-testing RAM: A practical alternative IEEE Design & Test of Computers 4 1 42 51 Feb. 1987
2. R. Dekker F. Beenker L. Thijssen A realistic self-test machine for static random access memories Proc. Int. Test Conf. (ITC) 353 361 Proc. Int. Test Conf. (ITC) 1988
3. A. J. van dc Goor Testing Semiconductor Memories: Theory and Practice 1991 John Wiley & Sons England, Chichester
4. B. F. Cockburn Y.-F. N. Sat Synthesized transparent BIST for detecting scrambled patternsensitive faults in RAMs Proc. Int. Test Conf. (ITC) 23 32 Proc. Int. Test Conf. (ITC) 1995-Oct.
5. J. Dreibelhis J. Barth H. Kalter R. Kho Processor-based built-in self-test for embedded DRAM IEEE Journal of Solid-State Circuits 1731 1740 Nov. 1998
6. C.-W. Wu Testing embedded memories; Is BIST the ultimate solution? Proc. Seventh IEEE Asian Test Symp, (ATS) 516 517 Proc. Seventh IEEE Asian Test Symp, (ATS) Singapore 1998-Dec.
7. C.-T. Huang J.-R. Huang C.-F. Wu C.-W. Wu T.-Y. Chang A programmable BIST core for embedded DRAM IEEE Design & Test of Computers 16 1 59 70 Jan.-Mar. 1999
8. O. Kebichi M. Nicolaidis A tool for automatic generation of BISTed and transparent BISTed RAMs Proc. IEEE Int. Conf. Computer Design (ICCD) 570 575 Proc. IEEE Int. Conf. Computer Design (ICCD) 1992-Oct.
9. R. Rajsuman RAMBIST builder: A methodology for automatic built-in self-test design of embedded RAMs Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT) 50 56 Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT) 1996
10. M. Marinescu Simple and efficient algorithms for functional RAM testing Proc. Int. Test Conf. (ITC) 236 239 Proc. Int. Test Conf. (ITC) 1982
11. K. Zarrineh S. J. Upadhyaya Programmable memory BIST and a new synthesis framework Proc. Int. Symp. Fault Tolerant Computing (FTCS) 352 355 Proc. Int. Symp. Fault Tolerant Computing (FTCS) Montreal 1999-June
12. K. Zarrineh S. J. Upadhyaya On programmable memory built-in self test architecutres Proc. Design, Automation and Test in Europe (DATE) 708 713 Proc. Design, Automation and Test in Europe (DATE) Paris 1999-Mar.
13. K.-J. Lin C.-W. Wu PMBC: a programmable BIST compiler for memory cores Third IEEE Int. Workshop on Testing Embedded Core-Based System-Chips P2.1 P2.6 Third IEEE Int. Workshop on Testing Embedded Core-Based System-Chips Dana Point 1999-Apr.
14. C.-F. Wu C.-T. Huang K.-L. Cheng C.-W. Wu Simulation-based test algorithm generation for random access memories Proc. IEEE VLSI Test Symp. (VTS) 291 296 Proc. IEEE VLSI Test Symp. (VTS) Montreal 2000-Apr.