Computer-aided test flow in core-based design

2000 22nd International Conference on Microelectronics, MIEL 2000 - Proceedings

Volumn 2, Issue , 1999, Pages 715-718

  Zivkovic, V A ^a   Tangelder, R J W T ^a   Kerkhoff, H G ^a  

^a UNIVERSITY OF TWENTE   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; DESIGN FOR TESTABILITY; FAULT TOLERANT COMPUTER SYSTEMS;

BOUNDARY SCAN TEST STANDARD; TEST PATTERN GENERATION; TIME TO MARKET REDUCTION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033299511     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/icmel.2000.838790     Document Type: Conference Paper

References (12)