Test vector decompression via cyclical scan chains and its application to testing core-based designs

IEEE International Test Conference (TC)

Volumn , Issue , 1998, Pages 458-464

  Jas, Abhijit ^a   Touba, Nur A ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE EQUIPMENT; DATA TRANSFER; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; VECTORS;

CORE BASED INTEGRATED CIRCUITS; TEST VECTOR DECOMPRESSION;

INTEGRATED CIRCUIT TESTING;

EID: 0032318126     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (22)