A programmable BIST core for embedded DRAM

IEEE Design and Test of Computers

Volumn 16, Issue 1, 1999, Pages 59-69

  Huang, Chih Tsun ^a,b   Huang, Jing Reng ^a   Wu, Chi Feng ^a   Wu, Cheng Wen ^a   Chang, Tsin Yuan ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b IEEE

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; DESIGN; DYNAMIC RANDOM ACCESS STORAGE; EMBEDDED SYSTEMS; TESTING;

REGISTER-TRANSFER-LANGUAGE LEVEL;

BUILT-IN SELF TEST;

EID: 0032680143     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.748806     Document Type: Article

References (10)

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3. R. Dekker, F. Beenker, and L. Thijssen, "A Realistic Self-Test Machine for Static Random Access Memories," Proc. Int'l Test Conf., IEEE Computer Society Press, Los Alamitos, Calif., 1988, pp. 353-361.
4. B. Nadeau-Dostie, A. Silburt, and V.K. Agarwal, "Serial Interface for Embedded-Memory Testing," IEEE Design & Test of Computers, Vol. 7, No. 2, Apr. 1990, pp. 52-63.
5. R. Treuer and V.K. Agarwal, "Built-In Self-Diagnosis for Repairable Embedded RAMs," IEEE Design & Test of Computers, Vol. 10, No. 2, June 1993, pp. 24-33.
6. P. Camurati et al., "Industrial BIST of Embedded RAMs," IEEE Design & Test of Computers, Vol. 12, No. 3, Fall 1995, pp. 86-95.
7. S. Tanoi et al., "On-Wafer BIST of a 200-Gb/s Failed-Bit Search for 1-Gb DRAM," IEEE J. Solid-State Circuits, Vol. 32, No. 11, Nov. 1997, pp. 1735-1742.
8. J. Dreibelbis et al., "Processor-Based Built-In Self-Test for Embedded DRAM," IEEE J. Solid-State Circuits, Vol. 33, No. 11, Nov. 1998, pp. 1731-1740.
9. R. Dekker, F. Beenker, and L. Thijssen, "Fault Modeling and Test Algorithm Development for Static Random Access Memories," Proc. Int'l Test Conf., IEEE CS Press, 1988, pp. 343-352.
10. A.J. van de Goor, "Using March Tests to Test SRAMs," IEEE Design & Test of Computers, Vol. 10, No. 1, Mar. 1993, pp. 8-14.