Scan chain design for test time reduction in core-based ICs

IEEE International Test Conference (TC)

Volumn , Issue , 1998, Pages 448-457

  Aerts, Joep ^a   Marinissen, Erik Jan ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

CORE BASED INTEGRATED CIRCUITS; SCAN CHAIN DESIGN; TEST VECTOR SETS;

FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; VECTORS;

INTEGRATED CIRCUIT TESTING;

EID: 0032314038     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.1998.743185     Document Type: Conference Paper

References (12)