Testing interconnects in a system chip

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2000, Pages 388-391

  Ravikumar, C P ^a   Chopra, Saurav ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONICS PACKAGING; GENETIC ALGORITHMS; GRAPH THEORY; INTERCONNECTION NETWORKS; PRINTED CIRCUIT BOARDS;

CHIP LEVEL INTERCONNECTS; SYSTEM-ON-CHIP;

PRINTED CIRCUIT TESTING;

EID: 0033897568     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)