Built-in self-test and self-diagnosis scheme for embedded SRAM

Proceedings of the Asian Test Symposium

Volumn , Issue , 2000, Pages 45-50

  Wang, Chih Wea ^a   Wu, Chi Feng ^a   Li, Jin Fu ^a   Wu, Cheng Wen ^a   Teng, Tony ^a   Chiu, Kevin ^a   Lin, Hsiao Ping ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

SELF DIAGNOSIS; STATIC RANDOM ACCESS MEMORY (SRAM);

BUILT-IN SELF TEST; ELECTRIC FAULT CURRENTS; EMBEDDED SYSTEMS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; MICROPROCESSOR CHIPS; RANDOM ACCESS STORAGE;

INTEGRATED CIRCUIT TESTING;

EID: 0034496878     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)

1. Y. Zorian, E. J. Marinissen, and S. Dey, "Testing embedded-core based system chips", in Proc. Int. Test Conf. (ITC), Oct. 1998, pp. 130-143.
2. B. F. Cockburn, "Tutorial on semiconductor memory testing", J. Electronic Testing: Theory and Application, vol. 5, pp. 321-336, 1994.
3. P. Camurati, P. Prinetto, M. S. Reorda, S. Barbagallo, A. Burri, and D. Medina, "Industrial BIST of embedded RAMs", IEEE Design & Test of Computers, vol. 12, no. 3, pp. 86-95, Fall 1995.
4. C.-W. Wu, 'Testing embedded memories: Is BIST the ultimate solution?", in Proc. Seventh IEEE Asian Test Symp. (ATS), Singapore, Dec. 1998, pp. 516-517.
5. C.-T. Huang, J.-R. Huang, C.-F. Wu, C.-W. Wu, and T.-Y. Chang, "A programmable BIST core for embedded DRAM", IEEE Design & Test of Computers, vol. 16, no. 1, pp. 59-70, Jan.-Mar. 1999.
6. R. Dekker, F. Beenker, and L. Thijssen, "Fault modeling and test algorithm development for static random access memories", in Proc. Int. Test Conf. (ITC), 1988, pp. 343-352.
7. A. J. van de Goor, "Using march tests to test SRAMs", IEEE Design & Test of Computers, vol. 10, no. 1, pp. 8-14, Mar. 1993.
8. R. P. Treuer and V. K. Agarwal, "Built-in self-diagnosis for repairable embedded RAMs", IEEE Design & Test of Computers, vol. 10, no. 2, pp. 24-33, June 1993.
9. I. Kim, Y Zorian, G. Komoriya, H. Pham, F. P. Higgins, and J. L. Lweandowski, "Built in self repair for embedded high density SRAM", in Proc. Int. Test Conf. (ITC), Oct. 1998, pp. 1112-1119.
10. C.-F. Wu, C.-T. Huang, and C.-W. Wu, "RAMSES: a fast memory fault simulator", in Proc. IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems (DFT), Albuquerque, Nov. 1999, pp. 165-173.
11. C.-F. Wu, C.-T. Huang, K.-L. Cheng, and C.-W. Wu, "Simulation-based test algorithm generation for random access memories", in Proc. IEEE VLSI Test Symp. (VTS), Montreal, Apr. 2000, pp. 291-296.
12. L. Shen and B. F. Cockburn, "An optimal march test for locating faults in DRAMs", in Proc. IEEE Int. Workshop on Memory Testing, 1993, pp. 61-66.
13. V. N. Yarmolik, Y. V. Klimets, A. J. van de Goor, and S. N. Demidenko, "RAM diagnostic tests", in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), 1996, pp. 100-102.
14. T. J. Bergfeld, D. Niggemeyer, and E. M. Rudnick, "Diagnostic testing of embedded memories using BIST", in Proc. Design, Automation and Test in Europe (DATE), Paris, Mar. 2000, pp 305-309.
15. C.-F. Wu, C.-T. Huang, C.-W. Wang, K.-L. Cheng, and C.-W. Wu, "Error catch and analysis for semiconductor memories using March tests", in Proc. IEEE Int. Conf. Computer-Aided Design (ICCAD), Nov. 2000 (to appear).