High-Level EDA environment for the automatic insertion of HD-BIST structures

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 16, Issue 3, 2000, Pages 179-184

  Benso, Alfredo ^a   Cataldo, Silvia ^a   Chiusano, Silvia ^a   Prinetto, Paolo ^a,c   Zorian, Yervant ^b  

^a POLITECNICO DI TORINO   (Italy)

^b LogicVision Inc   (United States)

^c UNIVERSITY OF ILLINOIS AT CHICAGO   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; NETWORK PROTOCOLS; PROGRAM COMPILERS; RAPID PROTOTYPING;

AUTOMATIC INSERTION; EMBEDDED CORES; HIERARCHICAL DISTRIBUTED BUILT-IN SELF TEST; SCHEDULING ALGORITHMS; SYSTEM-ON-CHIP APPLICATIONS;

BUILT-IN SELF TEST;

EID: 0033719992     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008326928340     Document Type: Article

References (5)

1. F. Beenker, R. Dekker, and R. Stans, "Implementing MACRO Test in Silicon Compiler Design," IEEE Design & Test of Computers, Vol. 7(2), pp. 41-51, April 1990.
2. O.F. Haberl and T. Kropf, "HIST, A Methodology for the Automatic Insertion of a Hierarchical Self Test," Proc. IEEE Int. Test Conference, 1992, pp. 732-741.
3. Y. Zorian, "A Distributed BIST Control Scheme for Complex VLSI Devices," Proc. IEEE VLSI Test Symposium, April 1993, pp. 4-9.
4. A. Benso, S. Chiusano, P. Prinetto, and Y. Zorian, "HD-BIST: A Hierarchical Framework for BIST Scheduling and Diagnosis in SoCs," Proc. IEEE Int. Test Conference, September 1999, pp. 993-1000.
5. http://grouper.ieee.org/groups/1500