Giant isotope effect in hot electron degradation of metal oxide silicon devices

IEEE Transactions on Electron Devices

Volumn 45, Issue 2, 1998, Pages 406-416

  Hess, Karl ^a   Kizilyalli, Isik C ^a   Lyding, Joseph W ^b  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b NOKIA RESEARCH CENTER   (United States)

Author keywords

Charge carrier processes; Cmos integrated circuits; Deuterium materials devices; Hydrogen materials devices; Mos devices; Semiconductor insulator interfaces; Transistors

Indexed keywords

ANNEALING; DEUTERIUM; ELECTRONS; HOT CARRIERS; HYDROGEN; INTERFACES (MATERIALS); ISOTOPES; PASSIVATION; SECONDARY ION MASS SPECTROMETRY;

GIANT ISOTOPE EFFECTS; HOT ELECTRON DEGRADATION;

CMOS INTEGRATED CIRCUITS;

EID: 0031999501     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.658674     Document Type: Article

References (60)

1. T. H. Ning, "Hot-electron emission from silicon into silicon dioxide," Solid-State Electron., vol. 21, pp. 273-282, 1973.
2. S. K. Lai, "Two-carrier nature of interface-state generation in hole trapping and radiation damage," Appl. Phys. Lett., vol. 39, no. 1, pp. 58-60, 1981.
3. E. H. Poindexter, "Physical chemistry of hydrogeneous species in the Si-SiO2 system," A. Naturforsch, vol. 50a, pp. 653-665, 1995.
4. D. J. DiMaria, E. Cartier, and D. Arnold, "Impact ionization, trap creation, degradation and breakdown in silicon dioxide films in silicon," J. Appl. Phys., vol. 73, pp. 3367-3384, 1993;
5. and also D. J. DiMaria and E. Cartier, "Mechanism for stress-induced leakage currents in thin silicon dioxide films" J. Appl. Phys., vol. 78, pp. 3883-3894, 1995.
6. T. Matsuoka, S. Taguchi, H. Ohtsuka, K. Taniguchi, C. Hamaguchi, S. Kakimoto, and K. Uda, "Hot-carrier-induced degradation of N20-oxynitrided gate oxide N-MOSFET's," IEEE Trans. Electron Devices, vol. 43, pp. 1364-1373, 1996.
7. J. W. Lyding, K. Hess, and I. C. Kizilyalli, "Reduction of hot electron degradation in MOS transistors by deuterium processing," Appl. Phys. Lett., vol. 68, pp. 2526-2528, 1996.
8. I. C. Kizilyalli, J. W. Lyding and K. Hess, "Deuterium post-metal annealing of MOSFET's for improved hot carrier reliability," IEEE Electron Device Lett., vol. 18, pp. 81-83, 1997.
9. R. A. B. Devine, J.-L. Autran, W. L. Warren, K. L. Vanheusdan, and J.-C. Rostaing, Appl. Phys. Lett., vol. 70, p. 2999, 1997.
10. J. W. Lyding, T.-C. Shen, J. S. Hubacek, J. R. Tucker, and G. C. Abeln, "Nanoscale patterning and oxidation of H-passivated Si(100)-2x1 surfaces with an ultrahigh vacuum scanning tunneling microscope," Appl. Phys. Lett., vol. 64, p. 2010, 1994.
11. T.-C. Shen, C. Wang, G. C. Abeln, J. R. Tucker, J. W. Lyding, Ph. Avouris, and R. E. Walkup, "Atomic-scale desorption through electronic and vibrational excitation mechanisms," Science, vol. 268, p. 1590, 1995.
12. E. T. Foley, A. F. Kam, J. W. Lyding, and Ph. Avouris, "Cryogenic UHV-STM study of hydrogen and deuterium desorption from Si(lOO)," Phys. Rev. Lett., to be published.
13. R. E. Walkup, D. M. Newns, and Ph. Avouris, Atomic and Nanometer-Scale Modification of Materials: Fundamentals and Applications, Ph. Avouris, Ed. Norwell, MA: Kluwer, 1993, pp. 97-109.
14. Ph. Avouris, R. E. Walkup, A. R. Rossi, T.-C. Shen, G. Abeln, J. R. Tucker, and J. W. Lyding, "STM-induced H atom desorption: Isotope effects and site selectivity," Chem. Phys. Lett., vol. 257, p. 148, 1996.
15. D. Menzel and R. Corner, J. Chem, Phys., vol. 41, p. 331, 1964.
16. P. Redhead, Can. J. Phys., vol. 42, p. 886, 1964.
17. P. von Allmen, K. Hess, J. W. Lyding, and I. C. Kizilyalli, "Theoretical study of hydrogen and deuterium desorption from a passivated Si (100) surface," in P roc. Int. Conf. Quantum Devices and Circuits 1997, pp. 49-56.
18. Chris G. Van de Walle and W. B. Jackson, "Comment on reduction of hot electron degradation in metal oxide semiconductor transistors by deuterium processing," [Appl. Phys. Lett. vol. 68, p. 2526, 1996] Appl. Phys. Lett., vol. 69, p. 2441, 1996.
19. M. Song and K. P. Mac Williams, "Comparison of NMOS and PMOS hot carrier effects from 300 to 77 K," IEEE Trans. Electron Devices, vol. 44, p. 268, 1997.
20. G. Cheroff, F. Fang, and H. Hochberg, "Effect of low temperature annealing on the surface conductivity of Si in the Si-SiO2-Al system," IBM J., vol. 8, pp. 416-421, 1964.
21. P. Balk, "Effects of hydrogen annealing on silicon surfaces," in Electrochem. Soc. Spring Meet., Abstr. no. 109, 1965, pp. 237-240.
22. N. M. Johnson, D. K. Biegeisen, and M. D. Moyer, "Low-temperature annealing and hydrogénation of defects at the Si-SiC>2 interface," J. Vac. Sei. Technol, vol. 19, pp. 390-394, 1981.
23. A. S. Grove, Physics and Technology of Semiconductor Devices. New York: Wiley, 1967.
24. E. H. Nicollian and J. R. Brews, MOS (Metal Oxide Semiconductor) Physics and Technology. New York: Wiley, 1982.
25. K. L. Brower, "Dissociation kinetics of hydrogen passivated (111) Si-SiO2 interface defects," Phys. Rev. B, vol. 42, pp. 3444-3453, 1990.
26. E. Cartier, J. H. Stathis, and D. A. Buchanan, "Passivation and depassivation of silicon dangling bonds at the Si-SiC>2 interface by atomic hydrogen," Appl. Phys. Lett., vol. 63, pp. 1510-1512, 1993.
27. E. H. Poindexter, E. R. Ahlstrom, and P. J. Caplan, "ESR centers and charge defects near the Si-SiC>2 interface," in The Physics o/SiC>2 and its Interfaces, S. T. Pantelides, Ed. New York: Pergamon, 1978, pp. 227-231.
28. C. M. Svensson, "The defect structure of the Si-SiO2 interface: A model based on trivalent silicon and its hydrogen compounds," in The Physics o/SiC>2 and its Interfaces, S. T. Pantelides Ed. New York: Pergamon, 1978, pp. 328-332.
29. B. J. Fishbein, J. T. Watt, and J. D. Plummer, "Time resolved annealing of interface traps in polysilicon gate metal-oxide-silicon capacitors," J. Electrochem. Soc.: Solid-State Sei. and Technol., vol. 134, pp. 674-681, 1987.
30. H. Fukuda, T. Ueno, H. Kawarada, and I. Ohdomari, "Effect of deuterium anneal on SiO2/Si(100) interface traps and electron spin resonance signals of ultrathin SiO2 films," Jpn. J. Appl. Phys., vol. 32, pp. L569-L571, 1993.
31. D. R. Collins, "Excess current generation due to reverse bias p-n junction stress," Appl. Phys. Lett., vol. 13, pp. 264-266, 1968.
32. B. A. McDonald, "Avalanche degradation of hfe," IEEE Trans. Electron Devices, vol. ED17, pp. 871-878, 1970.
33. E. H. Nicollian, C. N. Berglund, P. F. Schmidt, and J. M. Andrews, "Electrochemical charging of thermal SiO2 films by injected electron currents," J. Appl. Phys., vol. 42, pp. 5654-5664, 1971.
34. S. A. Abbas and R. C. Dockerty, "Hot carrier instability in IGFET's," Appl. Phys. Lett., vol. 27, pp. 147-148, 1975.
35. R. C. Sun, J. T. Clemens, and J. T. Nelson, "Effects of silicon nitride encapsulation on MOS device stability," in P roc. IEEE Int. Reliab. Phys. Symp., 1980, pp. 244-251.
36. Y. Leblebici and S. M. Kang, Hot-Carrier Reliability of MOS VLSI Circuits. Norwell, MA: Kluwer, 1993.
37. T. H. Ning, C. M. Osburn, and H. N. Yu, "Emission probability of hot electrons from silicon to silicon dioxide," J. Appl. Phys., vol. 48, pp. 286-293, 1977.
38. P. Lall, M. G. Pecht, and E. B. Hakim, Influence of Temperature on Microelectronics and System Reliability. New York: CRC, 1997, pp. 91-94.
39. D. J. DiMaria and J. W. Stasiak, "Trap creation in silicon dioxide produced by hot electrons," J. Appl. Phys., vol. 65, pp. 2342-2356, 1989. [39] B. Weir, D. Monroe, TDDB, Bell Labs Technical Memorandum, 1996. [40] E. H. Poindexter and G. J. Gerardi, Colloids and Surfaces, vol. 45, pp. 213-224, 1990.
40. C. Hu, S. C. Tarn, F. Hsu, P. Ko, T. Chan, K. W. Terrill, "Hot-electroninduced MOSFET degradation: Model, monitor, and improvement," IEEE Trans. Electron Devices, vol. ED32, pp. 375-385, 1985.
41. M. L. Chen, C. W. Leung, W. T. Cochran, W. Juengling, C. Dzuiba, and T. Yang, "Suppression of hot carrier effects in deep submicrometer CMOS technology," IEEE Trans. Electron Devices, vol. 35, pp. 2210-2220, 1988.
42. A. Schwein, W. Hansch, and W. Weber, "The relationship between oxide charge and device degradation: A comparative study of n- and p-channel MOSFET's," IEEE Trans. Electron Devices, vol. ED34, pp. 2493-2500, 1987.
43. P. Heremans, G. Van Den Bosch, R. Bellens, G. Groeseneken, and H.E. Maes, "Temperature dependence of the channel hot-carrier degradation of n-channel MOSFET's," IEEE Trans. Electron Devices, vol. 37, pp. 980-993, 1990.
44. B. Doyle, M. Bourcerie, J. Marchetaux, and A. Boudou, "Interface state creation and charge trapping in the medium-to-high gate voltage range during hot-carrier stressing of N-MOS transistors," IEEE Trans. Electron Devices, vol. 37, pp. 744-754, 1990.
45. S. Ogura, P. J. Tsang, W. W. Walker, D. Critchlow, and J. F. Shephard, "Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistor," IEEE Trans. Electron Devices, vol. ED27, pp. 1359-1367, 1980.
46. P. J. Tsang, S. Ogura, W. W. Walker, J. F. Shepard, and D. L. Critchlow, "Fabrication of high-performance LDDFET's with oxide sidewall-spacer technology," IEEE Trans. Electron Devices, vol. ED29, pp. 590-596, 1982.
47. P. K. Chatterjee, A. H. Shah, Y. Lin, W. R. Hunter, E. A. Walker, C. C. Rhodes, and W. C. Bruncke, "Enhanced performance 4A' X 1 highspeed SRAM using optically defined submicrometer devices in selected circuits," IEEE Trans. Electron Devices, vol. ED29, pp. 700-706, 1982.
48. See any IEDM Tech. Dig. 1982-1996.
49. E. Takeda, N. Suzuki, and T. Hagiwara, "Device performance degradation due to hot-carrier injection at energies below the Si-SiO2 energy barrier," in IEEE IEDM Tech. Dig., 1983, pp. 396-399.
50. J. E. Chung, M. Jeng, J. E. Moon, P. Ko, and C. Hu, "Low-voltage hotelectron currents and degradation in deep-submicrometer MOSFET's," IEEE Trans. Electron Devices, vol. 37, pp. 1651-1657, 1990.
51. M. Rodder, S. Aur, and I. C. Chen, "A scaled 1.8, 0.18-//m gate length CMOS technology: Device design and reliability considerations," in IEEE IEDM Tech. Dig., 1995, pp. 41518.
52. I. C. Kizilyalli and C. C. McAndrew, "Circuit technique to reduce hfe degradation in bipolar output drivers," IEEE Trans. Electron Devices, vol. 42, pp. 573-574, 1995.
53. Y. Leblebici and S. M. Kang, in Hot-carrier Reliability of MOS VLSI Circuits. Norwell, MA: Kluwer, 1993.
54. I. C. Kizilyalli, S. Lytle, B. R. Jones, E. Martin, S. Shive, A. Brooks, M. Thoma, R. Schanzer, J. Sniegowski, D. Wroge, R. Key, J. Kearney, and K. Stiles, "A very high performance and manufacturable 3.3 V 0.35fim CMOS technology for ASIC's," in IEEE CICC Tech. Dig., 1996, pp. 31-34.
55. I. C. Kizilyalli, M. J. Thoma, S. A. Lytle, E. P. Martin, R. Singh, S. C. Vitkavage, P. F. Bechtold, J. W. Kearney, M. Rambaud, M. Twiford, W. Cochran, L. Fenstermaker, R. Freyman, W. Sun, and A. Duncan, "High performance 3.3 and 5 V 0.5-ftm CMOS technology for ASIC's," IEEE Trans. Semiconduct. Manufact., vol. 8, pp. 440148, 1995.
56. J. Lee, S. Aur, R. Eklund, K. Hess, and J. W. Lyding, unpublished.
57. H. Park and C.R. Helms, "The effect of annealing treatment on the distribution of deuterium in silicon and in silicon/silicon oxide systems," J. Electrochem. Soc., vol. 139, pp. 2042-2046, 1992.
58. J. D. Bude, A. Frommer, M. R. Pinto and G. R. Weber, "EEPROM/Flash sub-3.0-V drain-source bias hot carrier writing," in IEDM Tech. Dig., 1995, p. 989.
59. M. Brassington, "Semi-custom ASIC technology trends," in Proc. IEEE CICC, 1995, pp. 47-54.
60. I.C. Kizilyalli, unpublished.