메뉴 건너뛰기




Volumn 35, Issue 12, 1988, Pages 2210-2220

Suppression of Hot-Carrier Effects in Submicrometer CMOS Technology

Author keywords

[No Author keywords available]

Indexed keywords

SEMICONDUCTOR DEVICES, MOS; SEMICONDUCTOR MATERIALS--CHARGE CARRIERS;

EID: 0024121747     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.8795     Document Type: Article
Times cited : (45)

References (34)
  • 1
    • 0020125523 scopus 로고
    • Generation of interface states by hot hole injection in MOSFET's
    • H. Gesch, J. P. Leburton, and G. E. Dorda, “Generation of interface states by hot hole injection in MOSFET's,” IEEE Trans. Electron Devices, vol. ED-29, no. 5, pp. 913–918, 1982.
    • (1982) IEEE Trans. Electron Devices , vol.ED-29 , Issue.5 , pp. 913-918
    • Gesch, H.1    Leburton, J.P.2    Dorda, G.E.3
  • 3
    • 0022028660 scopus 로고
    • Hot-electron and hole-emission effects in short n-channel MOSFET's
    • K. R. Hofmann, C. Werner, W. Weber, and G. Dorda “Hot-electron and hole-emission effects in short n-channel MOSFET's,” IEEE Trans. Electron Devices, vol. ED-32, no. 3, pp. 691–699, 1985.
    • (1985) IEEE Trans. Electron Devices , vol.ED-32 , Issue.3 , pp. 691-699
    • Hofmann, K.R.1    Werner, C.2    Weber, W.3    Dorda, G.4
  • 5
    • 0000410102 scopus 로고
    • 2/Si capacitors: The effect of gate-induced strain
    • May
    • 2/Si capacitors: The effect of gate-induced strain,” Appl. Phys. Lett., vol. 48, no. 18, pp. 1208–1210, May 1986.
    • (1986) Appl. Phys. Lett. , vol.48 , Issue.18 , pp. 1208-1210
    • Hook, T.B.1    Ma, T.P.2
  • 6
    • 0022956802 scopus 로고
    • Mechanism of hot carrier induced degradation in MOSFET's
    • S. Baba, A. Kita, and J. Ueda, “Mechanism of hot carrier induced degradation in MOSFET's,” in IEDM Tech. Dig., pp. 734–737, 1986.
    • (1986) IEDM Tech. Dig. , pp. 734-737
    • Baba, S.1    Kita, A.2    Ueda, J.3
  • 7
    • 0022957458 scopus 로고
    • Investigation and reduction of hot electron induced punch-through (HEIP) effect in submicron P-MOSFET's
    • M. Koyanagi, A. G. Lewis, J. Zhu, R. A. Martin, T. Y. Huang, and J. Y. Chen, “Investigation and reduction of hot electron induced punch-through (HEIP) effect in submicron P-MOSFET's,” in IEDM Tech. Dig., pp. 722–725, 1986.
    • (1986) IEDM Tech. Dig. , pp. 722-725
    • Koyanagi, M.1    Lewis, A.G.2    Zhu, J.3    Martin, R.A.4    Huang, T.Y.5    Chen, J.Y.6
  • 8
    • 0022751618 scopus 로고
    • Analysis of the gate-voltage-dependent series resistance of MOSFET's
    • K. K. Ng and W. T. Lynch, “Analysis of the gate-voltage-dependent series resistance of MOSFET's,” IEEE Trans. Electron Devices, vol. ED-33, no. 7, pp. 965–972, 1986.
    • (1986) IEEE Trans. Electron Devices , vol.ED-33 , Issue.7 , pp. 965-972
    • Ng, K.K.1    Lynch, W.T.2
  • 9
    • 0022329875 scopus 로고
    • Relief of hot carrier constraint on submicron CMOS devices by use of buried channel structure
    • M. Nakahara, Y. Hiruta, T. Noguchi, M. Yoshida, K. Maeguchi, and K. Kanzaki, “Relief of hot carrier constraint on submicron CMOS devices by use of buried channel structure,” in IEDM Tech. Dig., pp. 238–241, 1985.
    • (1985) IEDM Tech. Dig. , pp. 238-241
    • Nakahara, M.1    Hiruta, Y.2    Noguchi, T.3    Yoshida, M.4    Maeguchi, K.5    Kanzaki, K.6
  • 12
    • 0022739538 scopus 로고
    • Buried and graded/buried LDD structures for improved hot-electron reliability
    • C.-Y. Wei, J. M. Pimbley, and Y. Nissan-Cohen, “Buried and graded/buried LDD structures for improved hot-electron reliability,” IEEE Trans. Electron Devices, vol. EDL-7, no. 6, pp. 380–382, 1986.
    • (1986) IEEE Trans. Electron Devices , vol.EDL-7 , Issue.6 , pp. 380-382
    • Wei, C.-Y.1    Pimbley, J.M.2    Nissan-Cohen, Y.3
  • 14
    • 0023548487 scopus 로고
    • The impact of gate-drain drain overlapped LDD (GOLD) for deep submicron VLSI's
    • R. Izawa, T. Kure, S. Iijima, and E. Takeda, “The impact of gate-drain drain overlapped LDD (GOLD) for deep submicron VLSI's,” in IEDM Tech. Dig., pp. 38–41, 1987.
    • (1987) IEDM Tech. Dig. , pp. 38-41
    • Izawa, R.1    Kure, T.2    Iijima, S.3    Takeda, E.4
  • 15
    • 0022987951 scopus 로고
    • A high performance submicron CMOS process with self-aligned channel-stop and punch-through implants (twin-tub V)
    • M.-L. Chen, C.-W. Leung, W. T. Cochran, R. Harney, A. Maury, and H. P. W. Hey, “A high performance submicron CMOS process with self-aligned channel-stop and punch-through implants (twin-tub V),” in IEDM Tech. Dig., pp. 256–259, 1986.
    • (1986) IEDM Tech. Dig. , pp. 256-259
    • Chen, M.-L.1    Leung, C.-W.2    Cochran, W.T.3    Harney, R.4    Maury, A.5    Hey, H.P.W.6
  • 16
    • 0023349450 scopus 로고
    • MINIMOS 3: A MOSFET simulator that includes energy balance
    • W. Hänsch and S. Selberherr, “MINIMOS 3: A MOSFET simulator that includes energy balance,” IEEE Trans. Electron Devices, vol. ED-34, no. 5, pp. 1074–1078, 1987.
    • (1987) IEEE Trans. Electron Devices , vol.ED-34 , Issue.5 , pp. 1074-1078
    • Hänsch, W.1    Selberherr, S.2
  • 17
    • 84945713471 scopus 로고
    • Hot-electron-induced MOSFET degradation—model, monitor and improvement
    • C. M. Hu, S. C. Tam, F. C. Hsu, P.-K. Ko, T.-Y. Chan, and K. W. Terrill, “Hot-electron-induced MOSFET degradation—model, monitor and improvement,” IEEE Trans. Electron Devices, vol. ED-32, no. 2, pp. 375–385, 1985.
    • (1985) IEEE Trans. Electron Devices , vol.ED-32 , Issue.2 , pp. 375-385
    • Hu, C.M.1    Tam, S.C.2    Hsu, F.C.3    Ko, P.-K.4    Chan, T.-Y.5    Terrill, K.W.6
  • 18
    • 0022605858 scopus 로고
    • Device characterization of 1.0 µm CMOS technology for logic and custom VLSI applications
    • L. V. Tran, R. Ashton, B. Jones, C. Lawrence, and D. McGillis, “Device characterization of 1.0 µm CMOS technology for logic and custom VLSI applications,” in CICC Tech. Dig., p. 46, 1986.
    • (1986) CICC Tech. Dig. , pp. 46
    • Tran, L.V.1    Ashton, R.2    Jones, B.3    Lawrence, C.4    McGillis, D.5
  • 20
    • 0023592425 scopus 로고
    • Radiation and hot-electron electron hardened MOS structures
    • E. F. daSilva Jr., Y. Nishioka, and T. P. Ma, “Radiation and hot-electron electron hardened MOS structures,” in IEDM Tech. Dig., pp. 848–849, 1987.
    • (1987) IEDM Tech. Dig. , pp. 848-849
    • daSilva, E.F.1    Nishioka, Y.2    Ma, T.P.3
  • 22
    • 0344927515 scopus 로고
    • Effects of silicon nitride encapsulation on MOS stability
    • R. C. Sun, J. T. Clemens, and J. T. Nelson, “Effects of silicon nitride encapsulation on MOS stability,” Proc. IRPS, p. 244, 1980.
    • (1980) Proc. IRPS , pp. 244
    • Sun, R.C.1    Clemens, J.T.2    Nelson, J.T.3
  • 23
    • 0022326744 scopus 로고
    • Trap generation in gate oxide layer of MOS structures encapsulated by silicon nitride
    • S. Fujita, Y. Uemoto, and A. Sasaki, “Trap generation in gate oxide layer of MOS structures encapsulated by silicon nitride,” in IEDM Tech. Dig., pp. 64–67, 1985.
    • (1985) IEDM Tech. Dig. , pp. 64-67
    • Fujita, S.1    Uemoto, Y.2    Sasaki, A.3
  • 25
    • 0022291576 scopus 로고
    • Hot-electron induced device degradation
    • F.-C. Hsu and K. Y. Chiu, “Hot-electron induced device degradation,” in Proc., VLSI Symp., p. 108, 1985.
    • (1985) Proc., VLSI Symp. , pp. 108
    • Hsu, F.-C.1    Chiu, K.Y.2
  • 26
    • 0020250962 scopus 로고
    • Attaining low moisture levels in hermetic packages
    • M. Whit, K. Striny, and R. Sammons, “Attaining low moisture levels in hermetic packages,” Proc. IRPS, p. 253, 1982.
    • (1982) Proc. IRPS , pp. 253
    • Whit, M.1    Striny, K.2    Sammons, R.3
  • 28
    • 0022290777 scopus 로고
    • Profiled lightly doped drain (PLDD) structure for high reliable N-MOSFET's
    • T. Toyoshima, N. Nihira, and K. Kanzaki, “Profiled lightly doped drain (PLDD) structure for high reliable N-MOSFET's,” in Proc. VLSI Symp., p. 118, 1985.
    • (1985) Proc. VLSI Symp. , pp. 118
    • Toyoshima, T.1    Nihira, N.2    Kanzaki, K.3
  • 29
    • 0022987950 scopus 로고
    • Power supply voltage for future CMOS VLSI in half and sub micrometer
    • M. Kakumu, M. Kinugawa, K. Hashimoto, and J. Matsunaga, “Power supply voltage for future CMOS VLSI in half and sub micrometer,” in IEDM Tech. Dig., pp. 399–402, 1986.
    • (1986) IEDM Tech. Dig. , pp. 399-402
    • Kakumu, M.1    Kinugawa, M.2    Hashimoto, K.3    Matsunaga, J.4
  • 31
    • 0023542548 scopus 로고
    • The impact of gate induced drain leakage current on MOSFET scaling
    • T. Y. Chan, P. K. Ko, and C. Hu, “The impact of gate induced drain leakage current on MOSFET scaling,” in IEDM Tech. Dig., pp. 718–721, 1987.
    • (1987) IEDM Tech. Dig. , pp. 718-721
    • Chan, T.Y.1    Ko, P.K.2    Hu, C.3
  • 32
    • 0023553867 scopus 로고
    • Corner-field induced drain leakage in thin oxide MOSFET's
    • C. Chang and J. Lien, “Corner-field induced drain leakage in thin oxide MOSFET's,” in IEDM Tech. Dig., pp. 714–717. 1987.
    • (1987) IEDM Tech. Dig. , pp. 714-717
    • Chang, C.1    Lien, J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.