High Performance 3.3- and 5-V 0.5-µm CMOS Technology for ASIC's

IEEE Transactions on Semiconductor Manufacturing

Volumn 8, Issue 4, 1995, Pages 440-448

  Lytle, Steve A ^a   Cochran, William T ^a   Thoma, Morgan J ^a   Kizilyalli, Isik C ^a   Martin, Edward P ^a   Vitkavage, Susan C ^a   Bechtold, Philip F ^a   Kearney, Joseph W ^a   Twiford, Michael S ^a   Duncan, Amanda ^a   Rambaud, Marta M ^b   Freyman, R ^b   Fenstermaker, Larry R ^b   Sun, Weishi ^c  

^a LUCENT TECHNOLOGIES   (United States)

^b AT&T Microelectronics ^*  (United States)

^c UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; HOT CARRIERS; MATHEMATICAL MODELS; MOSFET DEVICES; OSCILLATORS (ELECTRONIC); PERFORMANCE; RELIABILITY; SEMICONDUCTOR DEVICE MANUFACTURE; STATISTICAL METHODS; SUBSTRATES; TECHNOLOGY;

GATE LENGTH CONTROL; GATE OXIDE; HARD-MASK GATE PROCESSING; PACKING DENSITY; POLY-BUFFERED LOCOS ISOLATION; PROCESS FLUCTUATIONS;

CMOS INTEGRATED CIRCUITS;

EID: 0029408472     PISSN: 08946507     EISSN: 15582345     Source Type: Journal    
DOI: 10.1109/66.475186     Document Type: Article

References (11)

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