메뉴 건너뛰기




Volumn 29, Issue 4, 1982, Pages 700-706

Enhanced-Performance 4K × 1 High-Speed SRAM Using Optically Defined Submicrometer Devices in Selected Circuits

Author keywords

[No Author keywords available]

Indexed keywords

RAM;

EID: 0020115574     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1982.20765     Document Type: Article
Times cited : (5)

References (21)
  • 2
    • 0019075967 scopus 로고
    • The impact of scaling laws on the choice of n-channel or p-channel for MOS VLSI
    • Oct.
    • P. K. Chatterjee, W. R. Hunter, T. C. Holloway, and Y. T. Lin, “The impact of scaling laws on the choice of n-channel or p-channel for MOS VLSI,” IEEE Electron Device Lett., vol. EDL-1, pp. 220–223, Oct. 1980.
    • (1980) IEEE Electron Device Lett , vol.EDL-1 , pp. 220-223
    • Chatterjee, P.K.1    Hunter, W.R.2    Holloway, T.C.3    Lin, Y.T.4
  • 3
    • 0019282781 scopus 로고
    • On scaling MOS devices for VLSI
    • Oct. also “Limits to scaling MOS devices,” in Dig. Tech. Papers, 1981 Symp. on VLSI Technology (Maui, Hawaii), pp. 16–17, Sept. 1981
    • Y. A. El-Mansy, “On scaling MOS devices for VLSI,” in Proc. ICCC Conf. (Rye, NY), pp. 457–460, Oct. 1980; also “Limits to scaling MOS devices,” in Dig. Tech. Papers, 1981 Symp. on VLSI Technology (Maui, Hawaii), pp. 16–17, Sept. 1981.
    • (1980) Proc. ICCC Conf. (Rye, NY) , pp. 457-460
    • El-Mansy, Y.A.1
  • 4
    • 0019662594 scopus 로고
    • A new transmission line model for silicided diffusions; Impact on the performance of VLSI circuits
    • (Maui, Hawaii) Sept.
    • D. B. Scott, W. R. Hunter, and H. Shichijo, “A new transmission line model for silicided diffusions; Impact on the performance of VLSI circuits,” in Dig. Tech. Papers, 1981 Symp. on VLSI Technology (Maui, Hawaii), pp. 94–95, Sept. 1981.
    • (1981) Dig. Tech. Papers, 1981 Symp. on VLSI Technology , pp. 94-95
    • Scott, D.B.1    Hunter, W.R.2    Shichijo, H.3
  • 5
    • 0019717264 scopus 로고
    • A re-examination of practical scalability limits of n-channel and p-channel MOS devices for VLSI
    • Dec.
    • H. Shichijo, “A re-examination of practical scalability limits of n-channel and p-channel MOS devices for VLSI,” in 1981 IEDM Tech. Dig. (Washington, DC), Dec. 1981.
    • (1981) 1981 IEDM Tech. Dig. (Washington, DC)
    • Shichijo, H.1
  • 6
    • 0019603042 scopus 로고
    • Coupling capacitances for two-dimensional wires
    • Aug.
    • R. L. M. Dang and N. Shigyo, “Coupling capacitances for two-dimensional wires,” IEEE Electron Device Lett., vol. EDL-2, pp. 196–197, Aug. 1981.
    • (1981) IEEE Electron Device Lett , vol.EDL-2 , pp. 196-197
    • Dang, R.L.M.1    Shigyo, N.2
  • 13
    • 0018912465 scopus 로고
    • High-speed NMOS circuits made with X-ray lithography and reactive sputter etch
    • Jan.
    • P. I. Suciu, E. N. Fuls, and H. J. Boll, “High-speed NMOS circuits made with X-ray lithography and reactive sputter etch,” IEEE Electron Device Lett., vol. EDL-1, no. 1, pp. 10–11, Jan. 1980.
    • (1980) IEEE Electron Device Lett , vol.EDL-1 , Issue.1 , pp. 10-11
    • Suciu, P.I.1    Fuls, E.N.2    Boll, H.J.3
  • 14
    • 36749112381 scopus 로고
    • Fabrication of sub-micron polysilicon lines by conventional techniques
    • Apr.
    • K. H. Nicholas, H. E. Brockman, and I. J. Stempt, “Fabrication of sub-micron polysilicon lines by conventional techniques,” Appl. Phys. Lett., vol. 26, no. 7, pp. 398–399, Apr. 1975.
    • (1975) Appl. Phys. Lett. , vol.26 , Issue.7 , pp. 398-399
    • Nicholas, K.H.1    Brockman, H.E.2    Stempt, I.J.3
  • 15
    • 84937354593 scopus 로고
    • Sub-micron polysilicon gate MOS/SOS technology
    • Dec.
    • A. C. Ipri, “Sub-micron polysilicon gate MOS/SOS technology,” in 1978 IEDM Tech. Dig. (Washington, DC), pp. 46–49, Dec. 1978.
    • (1978) 1978 IEDM Tech. Dig. (Washington, DC) , pp. 46-49
    • Ipri, A.C.1
  • 18
    • 0019392817 scopus 로고
    • A new edge-defined approach for submicrometer MOSFET fabrication
    • Jan.
    • W. R. Hunter, T. C. Holloway, P. K. Chatterjee, and A. F. Tasch, Jr., “A new edge-defined approach for submicrometer MOSFET fabrication,” IEEE Electron Device Lett., vol. EDL-2, no. 1, pp. 4–6, Jan. 1981.
    • (1981) IEEE Electron Device Lett , vol.EDL-2 , Issue.1 , pp. 4-6
    • Hunter, W.R.1    Holloway, T.C.2    Chatterjee, P.K.3    Tasch, A.F.4
  • 19
    • 0019049847 scopus 로고
    • Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistor
    • Aug.
    • S. Ogura, P. J. Tsang, W. W. Walker, D. L. Critchlow, and J. F. Shepard, “Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistor,” IEEE Trans. Electron Devices, vol. ED-27, pp. 1359–1367, Aug. 1980.
    • (1980) IEEE Trans. Electron Devices , vol.ED-27 , pp. 1359-1367
    • Ogura, S.1    Tsang, P.J.2    Walker, W.W.3    Critchlow, D.L.4    Shepard, J.F.5
  • 20
    • 0018730804 scopus 로고
    • A quadruply self-aligned MOS (QSA MOS); A new short-channel high-speed high-density MOSFET for VLSI
    • Dec.
    • K. Ohta, K. Yamada, K. Shimizu, and Y. Tarui, “A quadruply self-aligned MOS (QSA MOS); A new short-channel high-speed high-density MOSFET for VLSI,” in 1979 IEDM Tech. Dig. (Washington, DC), pp. 581–584, Dec. 1979.
    • (1979) 1979 IEDM Tech. Dig. (Washington, DC) , pp. 581-584
    • Ohta, K.1    Yamada, K.2    Shimizu, K.3    Tarui, Y.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.