Interface State Creation And Charge Trapping In The Medium-To-High Gate Voltage Range (V D/2 ≥ V G ≥ V D) During Hot-Carrier Stressing Of N-Mos Transistors

IEEE Transactions on Electron Devices

Volumn 37, Issue 3, 1990, Pages 744-754

  Doyle, Brian ^a   Bourcerie, Marc ^b   Marchetaux, Jean Claude ^b   Boudou, Alain ^a  

^a HEWLETT PACKARD COMPANY   (United States)

^b Bull SA Les Clayes sous Bois ^*  (France)

Author keywords

[No Author keywords available]

Indexed keywords

OXIDES; SEMICONDUCTOR DEVICES, MOS; SEMICONDUCTOR MATERIALS--CHARGE CARRIERS;

CHARGE TRAPPING; DYNAMIC STRESS EXPERIMENTS; HOT CARRIER EFFECT (HCE); HOT-CARRIER STRESSING; INTERFACE STATE CREATION; N-MOS TRANSISTORS;

TRANSISTORS;

EID: 0025404777     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.47781     Document Type: Article

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