Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor

IEEE Transactions on Electron Devices

Volumn 27, Issue 8, 1980, Pages 1359-1367

  Ogura, Seiki ^a   Tsang, Paul J ^a   Walker, William W ^a   Critchlow, Dale L ^a   Shepard, Joseph F ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS - LARGE SCALE INTEGRATION;

LDD DEVICES; LIGHTLY DOPED DRAIN SOURCE;

TRANSISTORS, FIELD EFFECT;

EID: 0019049847     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1980.20040     Document Type: Article

References (23)

1. T. H. Ning, P. W. Cook, R. H. Dennard, C. M. Osburn, S. E. Schuster, and H. N. Yu, “1 µm MOSFET VLSI technology: Part IV-Hot-electron design constraints,” IEEE J. Solid-State Circuits, vol. SC-14, pp. 268–275, Apr. 1979.
2. P. E. Cottrell, R. R. Troutman, and T. H. Ning, “Hot electron emission in n-channel IGFET's,” IEEE J. Solid-State Circuits, vol. SC-14, pp. 442–455, Apr. 1979.
3. T. H. Ning, C. M. Osburn, and H. N. Yu, “Emission probability of hot electrons from silicon into silicon dioxide,” J. Appl. Phys., vol. 48, pp. 286–293, 1977.
4. S. A. Abbas and R. C. Dockerty, “Hot-carrier instability in IGFET's,” Appl. Phys. Lett., vol. 27, pp. 147–148, 1975.
5. H. Hara, Y. Okamoto, and H. Ohnuma, “A new instability in MOS transistors caused by hot electron and hole injection from drain avalanche plasma into gate oxide,” Japan. J. Appl. Phys., vol. 9, pp. 1103–1112, 1970.
6. J. Matsunaga and S. Kohyama, “Evidence for impact-ionized electron injection in substrate of n-channel MOS structures,” Appl. Phys. Lett., vol. 33, pp. 335–377,1978.
7. P. K. Chatterjee, “VLSI Dynamic MOS design constrains due to drain induced primary and secondary impact ionization,” in IEDM Tech. Dig., pp. 14–17,1979.
8. S. Kohyama, S. Mimura, and H. Iizuka, “Non-thermal carrier generation in MOS structures,” in 11th Conf. on Solid-State Devices-Tokyo, p. A-2-2, 1979.
9. R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. LeBlanc, “Design of ion implanted MOSFET's with very small physical dimensions,” IEEE J. Solid-State Circuits, vol. SC-9, pp. 256–268, Oct. 1974.
10. R. H. Dennard, F. H. Gaensslen, E. J. Walker, and P. W. Cook, “1 µm MOSFET VLSI technology: Part II=Device designs and characteristics for high-performance logic applications,” IEEE J. Solid-State Circuits, vol. SC-14, pp. 247–255, Apr. 1979.
11. H. N. Yu, A. Reisman, C. M. Osburn, and D. L. Critchlow, “1 µm MOSFET VLSI technology Part I-An overview,” IEEE J. Solid-State Circuit, vol. SC-14, pp. 240–246, Apr. 1979.
12. K. Saito, T. Morase, S. Sato, and U. Harada, “A new short channel MOSFET with lightly doped drain,” Denshi Tsushin Rengo Taikai (in Japanese), p. 220, Apr. 1978.
13. T. Yamaguchi, M. L. Lust, S. Ragsdave, and S. Sato, “Submicron channel MOS-IC technology,” in ISSC Dig. Tech. Papers, pp. 82–83, 1979.
14. P. E. Cottrell and E. M. Buturla, “Steady state analysis of field effect transistors via the finite element method,” in IEDM Tech. Dig., pp. 51–54,1975.
15. D. A. Antoniadis, S. E. Hansen, and R. W. Dutton, “SUPREMII-A program for IC process modeling and simulation,” Stanford Electronics Lab. Tech. Rep. 5019-2,1978.
16. G. W. Mahoney, A. J. Jimenez, H. Quassemzadeh, T. R. Scott, W. T. Weeks, and D. A. Mehta, “A statistical analysis program for computer-aided circuit design,” in Dig. Tech. Papers (IEEE Southeast-Conf.), p. c-1-1, 1973.
17. K. Ohta, K. Yamada, K. Shimizu, and Y. Tarui, “A quadruply self-aligned MOS (SQA MOS): A new short channel high speed high density MOSFET for VLSI,” in IEDM Tech. Dig., pp. 581–584, 1979.
18. A. Grove, Physics and Technology of Semiconductor Devices. New York: Wiley, 1967, p. 193.
19. R. R. Troutman, “VLSI limitations from drain induced barrier lowering,” IEEE J. Solid-State Circuits, vol, SC-14, pp. 383–391, Apr. 1979.
20. T. Toyabe, K. Yamaguchi, S. Asai, and M. S. Mock, “A numerical model of avalanche breakdown in MOSFET's,” IEEE Trans. Electron Devices, vol. ED-25, pp. 825–832, July 1978.
21. S. M. Sze, Physics of Semiconductor Devices. New York: Wiley, 1969, p. 113.
22. H. F. Wolf, Silicon Semiconductor Data. Oxford, England: Pergamon, 1969.
23. H. N. Kotecha, F. H. De La Moneda, and K. E. Beilstein, “Characterization of short and narrow channel effects for CAD-IGFET model,” in ISSCC Dig. Tech. Papers, pp. 42–43, 1977.