Physics of multiple-node charge collection and impacts on single-event characterization and soft error rate prediction

IEEE Transactions on Nuclear Science

Volumn 60, Issue 3, 2013, Pages 1836-1851

  Black, Jeffrey D ^a   Dodd, Paul E ^a   Warren, Kevin M ^b  

^a SANDIA NATIONAL LABORATORIES   (United States)

^b VANDERBILT UNIVERSITY   (United States)

Author keywords

Charge sharing; multiple bit upset; multiple cell upset; multiple node charge collection; single event testing; technology computer aided design

Indexed keywords

CHARGE COLLECTION; CHARGE SHARING; MULTIPLE BIT UPSET; MULTIPLE CELL UPSET; SINGLE-EVENT TESTING; TECHNOLOGY COMPUTER AIDED DESIGN;

COMPUTER AIDED DESIGN;

FORECASTING;

EID: 84879288603     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2013.2260357     Document Type: Article

References (96)

1. P. E. Dodd and L.W.Massengill, "Basic mechanisms and modeling of single event upset in digital microelectronics," IEEE Trans. Nucl. Sci., vol. 50, no. 3, pp. 583-602, Jun. 2003.
2. R. L.Woodruff and P. J. Rudeck, "Three-dimensional numerical simulation of single event upset of an SRAM cell," IEEE Trans. Nucl. Sci., vol. 40, no. 6, pp. 1795-1803, Dec. 1993.
3. B. D. Olson, D. R. Ball, K. M.Warren, L.W. Massengill, N. F. Haddad, S. E. Doyle, and D. McMorrow, "Simultaneous single event charge sharing and parasitic bipolar conduction in a highly-scaled SRAM design," IEEE Trans. Nucl. Sci., vol. 52, no. 6, pp. 2132-2136, Dec. 2005.
4. J. D. Black, D. R. Ball, W. H. Robinson, D. M. Fleetwood, R. D. Schrimpf, R. A. Reed, D. A. Black, K. M. Warren, A. D. Tipton, P. E. Dodd, N. F. Haddad, M. A. Xapsos, H. S. Kim, and M. Friendlich, "Characterizing SRAM single event upset in terms of single and multiple node charge collection," IEEE Trans. Nucl. Sci., vol. 55, no. 6, pp. 2943-2947, Dec. 2008.
5. L. R. Rockett, Jr., "Simulated SEU hardened scaled CMOS SRAM cell design using gated resistors," IEEE Trans. Nucl. Sci., vol. 39, no. 5, pp. 1532-1541, Oct. 1992.
6. R. Lacoe, "CMOS scaling, design principles and hardening-by-design methodologies," presented at the IEEE NSREC Short Course, Monterey, CA, USA, 2003.
7. D. Gong and C. Shen, "Full-TCAD device simulation of CMOS circuits with a novel half-implicit solver," presented at the SISPAD 2012, Denver, CO, USA, 2012.
8. J. R. Ahlbin, L. W. Massengill, B. L. Bhuva, B. Narasimham, M. J. Gadlage, and P. H. Eaton, "Single-event transient pulse quenching in advanced CMOS logic circuits," IEEE Trans. Nucl. Sci., vol. 56, no. 6, pp. 3050-3056, Dec. 2009.
9. E. Ibe, S. S. Chung, S.Wen, H. Yamaguchi, Y. Yahagi, H. Kameyama, S. Yamamoto, and T. Akioka, "Spreading diversity in multi-cell neutron-induced upsets with device scaling," presented at the IEEE Custom Integrated Circuits Conf. (CICC), San Jose, CA, USA, 2006.
10. L. W. Massengill, "SEU modeling and prediction techniques," presented at the IEEE NSREC Short Course, Snowbird, UT, USA, 1993.
11. C. M. Hsieh, P. C. Murley, and R. R. O'Brien, "A field-funneling effect on the colleciton of alpha-particle-generated carriers in silicon devices," IEEE Electron Device Lett., vol. 2, no. 4, pp. 103-105, Apr. 1981.
12. S. E. Kerns, L. W. Massengill, D. V. J. Kerns, M. L. Alles, T. W. Houston, H. Lu, and L. R. Hite, "Model for CMOS/SOI single-event vulnerability," IEEE Trans. Nucl. Sci., vol. 36, no. 6, pp. 2305-2310, Dec. 1989.
13. M. L. Alles, K. L. Jones, J. E. Clark, J. C. Lee, W. F. Kraus, S. E. Kerns, and L.W. Massengill, "SOI/SRAM rad-hard design using a predictive SEU device model," presented at the GOMAC Conf. Dig. Papers, Las Vegas, NV, USA, 1990.
14. S. Kirkpatrick, "Modeling diffusion and collection of charge from ionizing radiation in silicon devices," IEEE Trans. Electron Devices, vol. 26, no. 11, pp. 1742-1753, Nov. 1979.
15. F. B.McLean and T. R. Oldham, "Charge funneling in N- and P-type Si substrates," IEEE Trans. Nucl. Sci., vol. 29, no. 6, pp. 2018-2023, Dec. 1982.
16. P. E. Dodd, "Device simulation of charge collection and single-event upset," IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 561-575, Apr. 1996.
17. J. D. Black, "Pattern identification of multiple cell upsets in static random access memories to relate experimental test results to single event upset mechanisms," Vanderbilt Univ., Nashville, TN, USA, 2008.
18. T. L. Criswell, P. R. Measel, and K. L. Wahlin, "Single event upset testing with relativistic heavy ions," IEEE Trans. Nucl. Sci., vol. 31, no. 6, pp. 1559-1562, Dec. 1984.
19. J. B. Blake and R. Mandel, "On-orbit observations of single event upset in harris HM-6508 1 K RAMS," IEEE Trans. Nucl. Sci., vol. 33, no. 6, pp. 1616-1619, Dec. 1986.
20. Test Method for Alpha Source Accelerated Soft Error Rate, JEDEC Standard JESD89-2A, 2007.
21. R. Koga, S. D. Pinkerton, T. J. Lie, and K. B. Crawford, "Single-word multiple-bit upsets in static random access devices," IEEE Trans. Nucl. Sci., vol. 40, no. 6, pp. 1941-1946, Dec. 1993.
22. P. T. McDonald, W. J. Stapor, A. B. Campbell, and L. W. Massengill, "Non-random single event upset trends," IEEE Trans. Nucl. Sci., vol. 36, no. 6, pp. 2324-2329, Dec. 1989.
23. D. G. Mavis, P. H. Eaton, M. D. Sibley, R. C. Lacoe, E. J. Smith, and K. A. Avery, "Multiple bit upsets and errormitigation in ultra-deep submicron SRAMS," IEEE Trans. Nucl. Sci., vol. 55, no. 6, pp. 3288-3294, Dec. 2008.
24. Y. Song, K. N. Vu, J. S. Cable, A. A. Witteles, W. A. Kolasinski, R. Koga, J. H. Elder, J. V. Osborn, R. C. Martin, and N. M. Ghoniem, "Experimental and analytical investigation of single event, multiple bit upsets in poly-silicon load, NMOS SRAMs," IEEE Trans. Nucl. Sci., vol. 35, no. 6, pp. 1673-1677, Dec. 1988.
25. P. E. Dodd, F. W. Sexton, and P. S.Winokur, "Three-dimensional simulation of charge collection and multiple-bit upset in Si devices," IEEE Trans. Nucl. Sci., vol. 41, no. 6, pp. 2005-2017, Dec. 1994.
26. O. H. Musseau, F. Gardic, P. Roche, T. Corbiere, R. A. Reed, S. P. Buchner, P. T.McDonald, J. S. Melinger, L.H. Tran, andA. B. Campbell, "Analysis ofMultiple Bit Upsets (MBU) inCMOS SRAM," IEEE Trans. Nucl. Sci., vol. 43, no. 6, pp. 2879-2888, Dec. 1996.
27. Y. Kawakami, M. Hane, H. Nakamura, T. Yamada, and K. Kumagai, "Investigation of soft error rate including multi-bit upsets in advanced SRAM using neutron irradiation test and 3D mixed-mode device simulation," presented at the IEEE Int. Electron DevicesMeeting (IEDM), San Francisco, CA, USA, 2004.
28. R. Koga, W. A. Kolasinski, J. V. Osborn, J. H. Elder, and R. Chitty, "SEU test techniques for 256 K static RAMs and comparisons of upsets by heavy ions and protons," IEEE Trans. Nucl. Sci., vol. 35, no. 6, pp. 1638-1643, Dec. 1988.
29. P. E. Dodd, O. H. Musseau, M. R. Shaneyfelt, F. W. Sexton, C. D'hose, G. L. Hash, M. Martinez, R. A. Loemker, J.-L. Leray, and P. S. Winokur, "Impact of ion energy on single-event upset," IEEE Trans. Nucl. Sci., vol. 45, no. 6, pp. 2483-2491, Dec. 1998.
30. F. Wrobel, J.-M. Palau, M.-C. Calvet, O. Bersillon, and H. Duarte, "Simulation of nucleon-induced nuclear reactions in a simplified SRAM structure: Scaling effects on SEU and MBU cross sections," IEEE Trans. Nucl. Sci., vol. 48, no. 6, pp. 1946-1952, Dec. 2001.
31. K. Osada, K. Yamaguchi, Y. Saitoh, and T. Kawahara, "Cosmic-ray multi-error immunity for SRAM, based on analysis of the parasitic bipolar effect," presented at the 2003 Symp. VLSI Circuits, Kyoto, Japan, 2003.
32. N. Seifert, B. Gill, K. Foley, and P. Relangi, "Multi-cell upset probabilities of 45 nm high-k metal gate SRAM devices in terrestrial and space environments," presented at the IEEE Int. Reliab. Phys. Symp. (IRPS), Phoenix, AZ, USA, 2008.
33. G. Gasiot, D. Giot, and P. Roche, "Multiple cell upsets as the key contribution to the total SER of 65 nm CMOS SRAMs and its dependence on well engineering," IEEE Trans. Nucl. Sci., vol. 54, no. 6, pp. 2468-2473, Dec. 2007.
34. D. Giot, P. Roche, G. Gasiot, J.-L. Autran, and R. Harboe-Sorensen, "Heavy ion testing and 3-D simulations of multiple cell upset in 65 nm standard SRAMs," IEEE Trans. Nucl. Sci., vol. 55, no. 4, pp. 2048-2054, Aug. 2008.
35. G. Gasiot, S. Uznanski, and P. Roche, "SEE test and modeling results on 45 nm SRAMs with different well strategies," presented at the IEEE Int. Reliab. Phys. Symp. (IRPS), Anaheim, CA, USA, 2010.
36. T. Nakauchi, N. Mikami, A. Oyama, H. Kobayashi, H. Usui, and J. Kase, "A novel technique for mitigating neutron-induced multi-cell upset by means of back bias," presented at the IEEE Int. Reliab. Phys. Symp. (IRPS), Phoenix, AZ, USA, 2008.
37. G. Gasiot, P. Roche, and P. Flatresse, "Comparison of multiple cell upset response of bulk and SOI 130 nm technologies in the terrestrial environment," presented at the IEEE Int. Reliab. Phys. Symp. (IRPS), Phoenix, AZ, USA, 2008.
38. E. H. Cannon, M. S. Gordon, D. F. Heidel, A. J. KleinOsowski, P. Oldiges, K. P. Rodbell, and H. H. K. Tang, "Multi-bit upsets in 65 nm SOI SRAMs," in IEEE Int. Reliab. Phys. Symp. (IRPS), Phoenix, AZ, USA, 2008.
39. C. I. Underwood, J. W. Ward, C. S. Dyer, and A. J. Sims, "Observations of single-event upsets in non-hardened high-density SRAMs in sun-synchronous orbit," IEEE Trans. Nucl. Sci., vol. 39, no. 6, pp. 1817-1828, Dec. 1992.
40. R. A. Reed, M. A. Carts, P. W. Marshall, C. J. Marshall, O. H. Musseau, P. J. McNulty, D. R. Roth, S. P. Buchner, J. S. Melinger, and T. Corbiere, "Heavy ion and proton-induced single event multiple upset," IEEE Trans. Nucl. Sci., vol. 44, no. 6, pp. 2224-2229, Dec. 1997.
41. A. B. Campbell, O.Musseau, V. Ferlet-Cavrois, W. J. Stapor, and P. T. McDonald, "Analysis of single event effects at grazing angle," IEEE Trans. Nucl. Sci., vol. 45, no. 3, pp. 1603-1611, Jun. 1998.
42. N. Ikeda, S. Kuboyama, S. Matsuda, and T. Handa, "Analysis of angular dependence of proton-induced multiple-bit upsets in a synchronous SRAM," IEEE Trans. Nucl. Sci., vol. 52, no. 6, pp. 2200-2204, Dec. 2005.
43. A. D. Tipton, J. A. Pellish, R. A. Reed, R. D. Schrimpf, R. A. Weller, M. H. Mendenhall, B. D. Sierawski, A. K. Sutton, R. M. Diestelhorst, G. A. Espinel, J. D. Cressler, P.W.Marshall, and G. Vizkelethy, "Multiple- bit upset in 130 nm CMOS technology," IEEE Trans. Nucl. Sci., vol. 53, no. 6, pp. 3259-3264, Dec. 2006.
44. A. D. Tipton, J. A. Pellish, J. M. Hutson, R. C. Baumann, X. Deng, A. Marshall, M. A. Xapsos, H. S. Kim, M. R. Friendlich, M. J. Campola, C. M. Seidleck, K. A. LaBel, M. H. Mendenhall, and Reed, "Device- orientation effects on multiple-bit upset in 65 nm SRAMs," IEEE Trans. Nucl. Sci., vol. 55, no. 6, pp. 2880-2885, Dec. 2008.
45. J. Maiz, S. Hareland, K. Zhang, and P. Armstrong, "Characterization of multi-bit soft error events in advanced SRAMs," presented at the IEEE Int. Electron Devices Meet. (IEDM), Washington DC, USA, 2003.
46. J. A. Zoutendyk, L. D. Edmonds, and L. S. Smith, "Characterization of multiple-bit errors from single-ion tracks in integrated circuits," IEEE Trans. Nucl. Sci., vol. 36, no. 6, pp. 2267-2274, Dec. 1989.
47. V. Ferlet-Cavrois, P. Paillet, J. R. Schwank, G. Vizkelethy, M. R. Shaneyfelt, J. Baggio, A. Torres, and O. Flament, "Charge collection by capacitive influence through isolation oxides," IEEE Trans. Nucl. Sci., vol. 50, no. 6, pp. 2208-2218, Dec. 2003.
48. T. J. O'Gorman, "The effect of cosmic rays on the soft error rate of a DRAM at ground level," IEEE Trans. Electron Devices, vol. 41, no. 4, pp. 553-557, Apr. 1994.
49. L. W. Massengill, "Cosmic and terrestrial single-event radiation effects in dynamic random access memories," IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 576-593, Apr. 1996.
50. J.-S. Chern, P. Yang, P. Pattnaik, and J. A. Seitchik, "Alpha-particle induced charge transport between closely spaced memory cells," IEEE Trans. Electron Devices, vol. 33, no. 6, pp. 822-834, Jun. 1986.
51. K. A. LaBel, P.W. Marshall, J. L. Barth, R. B. Katz, R. A. Reed, H. W. Leidecker, H. S. Kim, and C. J. Marshall, "Anatomy of an in-flight anomaly: Investigation of proton-induced SEE test results for stacked IBM DRAMs," IEEE Trans. Nucl. Sci., vol. 45, no. 6, pp. 2898-2903, Dec. 1998.
52. J. Benedetto, J. Black, and G. Ott, "Soft error case study: Single Event Functional Interrupts (SEFIs) in COTS SDRAMs," presented at the IEEE NSREC Short Course, Tucson, AZ, USA, 2008.
53. G. M. Swift and S. M. Guertin, "In-flight observations of multiple- bit upset in DRAMs," IEEE Trans. Nucl. Sci., vol. 47, no. 6, pp. 2386-2391, Dec. 2000.
54. A. Makihara, H. Shindou, N. Nemoto, S. Kuboyama, S. Matsuda, T. Oshima, T. Hirao, H. Itoh, S. P. Buchner, and A. B. Campbell, "Analysis of single-ion multiple-bit upset in high-density DRAMs," IEEE Trans. Nucl. Sci., vol. 47, no. 6, pp. 2400-2404, Dec. 2000.
55. S. P. Buchner, A. B. Campbell, R. A. Reed, B. Fodness, and S. Kuboyama, "Angular dependence of multiple-bit upsets induced by protons in a 16 Mbit DRAM," IEEE Trans. Nucl. Sci., vol. 51, no. 6, pp. 3270-3277, Dec. 2004.
56. G. Cellere, A. Paccagnella, A. Visconti, M. Bonanomi, R. Harboe-Sorensen, and A. Virtanen, "Angular dependence of heavy ion effects in floating gate memory arrays," IEEE Trans. Nucl. Sci., vol. 54, no. 6, pp. 2371-2378, Dec. 2007.
57. K. Grurmann, D.Walter, M. Herrmann, F. Gliem, H. Kettunen, and V. Ferlet-Cavrois, "SEU and MBU angular dependence of samsung and micron 8-Gbit SLC NAND-flash memories under heavy-ion irradiation," presented at the IEEE Radiat. Effects DataWorkshop, Las Vegas, NV, USA, 2011.
58. M. Bagatin, S. Gerardin, A. Paccagnella, and V. Ferlet-Cavrois, "Single and multiple cell upsets in 25-nm NAND flash memories," IEEE Trans. Nucl. Sci., to be published.
59. M. N. Liu and S. Whitaker, "Low power SEU immune CMOS memory circuits," IEEE Trans. Nucl. Sci., vol. 39, no. 6, pp. 1679-1684, Dec. 1992.
60. S. Kuboyama, "Single-event-effect tolerant SOI-based inverter, NAND element, NOR element, semiconductor memory device and data latch circuit," U.S. Patent 7504850, Mar. 17, 2009.
61. T. Calin, M. Nicolaidis, and R. Velazco, "Upset hardened memory design for submicron CMOS technology," IEEE Trans. Nucl. Sci., vol. 43, no. 6, pp. 2874-2878, Dec. 1996.
62. D. G. Mavis and P. H. Eaton, "Soft error rate mitigation techniques for modern microcircuits," presented at the IEEE Int. Reliab. Phys. Symp. (IRPS), Dallas, TX, USA, 2002.
63. K. M. Warren, B. D. Sierawski, R. A. Reed, R. A. Weller, C. H. Carmichael, A. Lesea, M. H. Mendenhall, P. E.Dodd, R. D. Schrimpf, L. W. Massengill, T. Hoang, H. Wan, J. L. De Jong, R. Padovani, and Fabula, "Monte-Carlo based on-orbit single event upset rate prediction for a radiation hardened by design latch," IEEE Trans. Nucl. Sci., vol. 54, no. 6, pp. 2419-2425, Dec. 2007.
64. K.M.Warren, A. L. Sternberg, R. A. Weller, M.P. Baze, L.W. Massengill, R. A. Reed, M. H. Mendenhall, and R. D. Schrimpf, "Integrating circuit level simulation and Monte-Carlo radiation transport code for single event upset analysis in SEU hardened circuitry," IEEE Trans. Nucl. Sci., vol. 55, no. 6, pp. 2886-2894, Dec. 2008.
65. A. J. Tylka, J. H. J. Adams, P. R. Boberg, B. Brownstein, W. F. Dietrich, E. O. Flueckiger, E.L. Petersen, M.A. Shea, D.F. Smart, and E. C. Smith, "CREME96: A revision of the cosmic ray effects on micro-electronics code," IEEE Trans. Nucl. Sci., vol. 44, no. 6, pp. 2150-2160, Dec. 1997.
66. M. P. Baze, B. W. Hughlock, J. L. Wert, J. Tostenrude, L. W. Massengill, O. A. Amusan, R. C. Lacoe, K. Lilja, and M. B. Johnson, "Angular dependence of single event sensitivity in hardened flip/flop designs," IEEE Trans. Nucl. Sci., vol. 55, no. 6, pp. 3295-3301, Dec. 2008.
67. K. P. Rodbell, D. F. Heidel, J. A. Pellish, P. W. Marshall, H. H. K. Tang, C. E.Murray, K. A. LaBel, M. S. Gordon, K. G. Stawiasz, J. R. Schwank, M. D. Berg, H. S. Kim, M. R. Friendlich, A. M. Phan, and C. M. Seidlock, "32 and 45 nm Radiation-Hardened-by-Design (RHBD) SOI latches," IEEE Trans. Nucl. Sci., vol. 58, no. 6, pp. 2702-2710, Dec. 2011.
68. R. Velazco, T. Calin, M. Nicolaidis, S. C. Moss, S. D. LaLumondiere, L. H. Tran, and R. Koga, "SEU-hardened storage cell validation using a pulsed laser," IEEE Trans. Nucl. Sci., vol. 43, no. 6, pp. 2843-2848, Dec. 1996.
69. J.D.Black, A.L. Sternberg, M. L. Alles, A.F. Witulski, B. L. Bhuva, L. W. Massengill, J. M. Benedetto, M. P. Baze, J. L.Wert, and M. G. Hubert, "HBD layout isolation techniques formultiple node charge collection mitigation," IEEE Trans. Nucl. Sci., vol. 52, no. 6, pp. 2536-2541, Dec. 2005.
70. O. A. Amusan, A. F. Witulski, L. W. Massengill, B. L. Bhuva, P. R. Fleming, M. L. Alles, A. L. Sternberg, J. D. Black, and R.D. Schrimpf, "Charge collection and charge sharing in a 130 nmCMOS technology," IEEE Trans. Nucl. Sci., vol. 53, no. 6, pp. 3253-3258, Dec. 2006.
71. O. A. Amusan, L. W. Massengill, M. P. Baze, B. L. Bhuva, A. F. Witulski, S. DasGupta, A. L. Sternberg, P. R. Fleming, C. C. Heath, and M. L. Alles, "Directional sensitivity of single event upsets in 90 nm CMOS due to charge sharing," IEEE Trans. Nucl. Sci., vol. 54, no. 6, pp. 2584-2589, Dec. 2007.
72. D. Rossi, M. Omana, F. Toma, and C.Metra, "Multiple transient faults in logic: An issue for next generation ICs?," presented at the IEEE Int. Symp. Defect and Fault Tolerance in VLSI Syst., Monterey, CA, USA, 2005.
73. C. Rusu, A. Bougerol, L. Anghel, C. Weulerse, N. Buard, S. Benhammadi, N. Renaud, G. Hubert, F. Wrobel, T. Carriere, and R. Gaillard, "Multiple event transient induced by nuclear reactions in CMOS logic cells," presented at the IEEE Int. On-Line Testing Symp. (IOLTS), Crete, Greece, 2007.
74. L. W. Massengill and P. W. Tuinenga, "Single-event transient pulse propagation in digital CMOS," IEEE Trans. Nucl. Sci., vol. 55, no. 6, pp. 2861-2871, Dec. 2008.
75. J. R. Ahlbin, M. J. Gadlage, D. R. Ball, A. F.Witulski, B. L. Bhuva, R. A. Reed, G. Vizkelethy, and L.W.Massengill, "The effect of layout topology on single-event transient pulse quenching in a 65 nm bulk CMOS process," IEEE Trans. Nucl. Sci., vol. 57, no. 6, pp. 3380-3385, Dec. 2010.
76. N. M. Atkinson, J. R. Ahlbin, A. F. Witulski, N. J. Gaspard, W. T. Holman, B. L. Bhuva, E. X. Zhang, L. Chen, and L. W. Massengill, "Effect of transistor density and charge sharing on single-event transients in 90-nm bulk CMOS," IEEE Trans. Nucl. Sci., vol. 58, no. 6, pp. 2578-2584, Dec. 2011.
77. D. B. Limbrick, N. N. Mahatme, W. H. Robinson, and B. L. Bhuva, "Reliability-aware synthesis of combinational logic with minimal performance penalty," IEEE Trans. Nucl. Sci., to be published.
78. N. Miskov-Zivanov and D. Marculescu, "Multiple transient faults in combinational and sequential circuits: A systematic approach," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 29, no. 10, pp. 1614-1627, Oct. 2007.
79. N. Seifert, V. Ambrose, B. Gill, Q. Shi, R. Allmon, C. Recchia, S. Mukherjee, N. Nassif, J. Krause, J. Pickholtz, and A. Balasubramanian, "On the radiation-induced soft error performance of hardened sequential elements in advanced bulk CMOS technologies," presented at the IEEE Int. Reliab. Phys. Symp. (IRPS), Anaheim, CA, USA, 2010.
80. H.-H. K. Lee, K. Lilja, M. Bounasser, P. Relangi, I. R. Linscott, U. S. Inan, and S. Mitra, "LEAP: Layout design through error-aware transistor positioning for soft-error resilient sequential cell design," presented at the IEEE Int. Reliab. Phys. Symp. (IRPS), Anaheim, CA, USA, 2010.
81. H.-H. K. Lee, K. Lilja, M. Bounasser, I. R. Linscott, and U. S. Inan, "Design framework for soft-error-resilient sequential cells," IEEE Trans. Nucl. Sci., vol. 58, no. 6, pp. 3026-3032, Dec. 2011.
82. T. Uemura, Y. Tosaka, H. Matsuyama, K. Shono, C. J. Uchibori, K. Takahisa, M. Fukuda, and K. Hatanaka, "SEILA: Soft error immune latch for mitigating multi-node-SEU and local-clock-SET," presented at the IEEE Int. Reliab. Phys. Symp. (IRPS), Anaheim, CA, USA, 2010.
83. A. T. Kelly, P. R. Fleming, W. T. Holman, A. F. Witulski, B. L. Bhuva, and L. W. Massengill, "Differential analog layout for improved ASET tolerance," IEEE Trans. Nucl. Sci., vol. 54, no. 6, pp. 2053-2059, Dec. 2007.
84. D. R. Blum and J. G. Delgado-Frias, "Hardened by design techniques for implementing multiple-bit upset tolerant static memories," presented at the IEEE Int. Symp. Circuits Syst. (ISCAS), New Orleans, LA, USA, 2007.
85. M. D'Alessio, M. Ottavi, and F. Lombardi, "Design of a nanometric CMOS memory cell for hardening to a single event with a multiple node upset," IEEE Trans. Device Mater. Relib., vol. PP, no. 99, pp. 1-6, 2012.
86. O. A. Amusan, L. W. Massengill, B. L. Bhuva, S. DasGupta, A. F. Witulski, and J. R. Ahlbin, "Design techniques to reduce set pulse widths in deep-submicron combinational logic," IEEE Trans. Nucl. Sci., vol. 54, no. 6, pp. 2060-2064, Dec. 2007.
87. B. Narasimham, J. W. Gambles, R. L. Shuler, B. L. Bhuva, and L. W. Massengill, "Quantifying the effect of guard rings and guard drains in mitigating charge collection and charge spread," IEEE Trans. Nucl. Sci., vol. 55, no. 6, pp. 3456-3460, Dec. 2008.
88. R. Harboe-Sorensen, F.-X. Guerre, J.-G. Loquet, and C. Tizon, "Heavy-ion single-event effects testing of lead-on-chip assembled high-density memories," IEEE Trans. Nucl. Sci., vol. 50, no. 6, pp. 2322-2327, Dec. 2003.
89. G. Gasiot, D. Giot, and P. Roche, "Alpha-induced multiple cell upsets in standard and radiation hardened SRAMs manufactured in a 65 nm CMOS technology," IEEE Trans. Nucl. Sci., vol. 53, no. 6, pp. 3479-3486, Dec. 2006.
90. E. L. Petersen, "Single-event data analysis," IEEE Trans. Nucl. Sci., vol. 55, no. 6, pp. 2819-2841, Dec. 2008.
91. G. Hubert, N. Buard, C. Weulersse, T. Carriere, M.-C. Palau, J.-M. Palau, D. Lambert, J. Baggio, F. Wrobel, F. Saigne, and R. Gaillard, "A review of DASIE code family: Contribution to SEU/MBU understanding," presented at the IEEE Int. On-Line Testing Symp. (IOLTS), Saint-Raphaël, France, 2005.
92. S. Yoshimoto, T. Amashita, M. Yoshimura, Y. Matsunaga, H. Yasuura, S. Izumi, H. Kawaguchi, and M. Yoshimoto, "Neutron-induced soft error rate estimation for SRAM using PHITS," presented at the IEEE Int. On-Line Testing Symp. (IOLTS), Sitges, Spain, 2012.
93. D. E. Fulkerson, D. K. Nelson, and R. M. Carlson, "Boxes: An engineering methodology for calculating soft error rates in SOI integrated circuits," IEEE Trans. Nucl. Sci., vol. 53, no. 6, pp. 3329-3335, Dec. 2006.
94. W. F. Heidergott, "System level mitigation strategies," presented at the IEEE NSREC Short Course, Norfolk, VA, USA, 1999.
95. P. Reviriego, J. A. Maestro, and C. Cervantes, "Reliability analysis of memories suffering multiple bit upsets," IEEE Trans. Device Mater. Relib., vol. 7, no. 4, pp. 592-601, Dec. 2007.
96. T. R. Oldham, M. R. Friendlich, E. P. Wilcox, K. A. LaBel, S. P. Buchner, D. McMorrow, D. G. Mavis, P. H. Eaton, and J. Castillo, "Correlation of laser test results with heavy ion results for NAND flash memory," IEEE Trans. Nucl. Sci., vol. 59, no. 6, pp. 2831-2836, Dec. 2012.