Analysis of multiple bit upsets (MBU) in a cmos sram

IEEE Transactions on Nuclear Science

Volumn 43, Issue 6 PART 1, 1996, Pages 2879-2888

  Musseau, O ^a   Gardic, F ^a   Roche, P ^a   Corbiere T ^b   Reed, R A ^b   Buchner, S ^b   McDonald, P ^c   Melinger, J ^c   Tran, L ^d   Campbell, A B ^d  

^a CEA DIF   (France)

^b Route de Gachet BP70602 44306 3   (France)

^c NAVAL RESEARCH LABORATORY   (United States)

^d SFA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ENERGY TRANSFER; ION BOMBARDMENT; PULSED LASER APPLICATIONS; RADIATION EFFECTS; SEMICONDUCTOR DEVICE TESTING;

LINEAR ENERGY TRANSFER (LET); MULTIPLE BIT UPSETS (MBU); STATIC RANDOM ACCESS MEMORY (SRAM);

RANDOM ACCESS STORAGE;

EID: 0030370399     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/23.556881     Document Type: Article

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