Directional sensitivity of single event upsets in 90 nm CMOS due to charge sharing

IEEE Transactions on Nuclear Science

Volumn 54, Issue 6, 2007, Pages 2584-2589

  Amusan, Oluwole A ^a,b   Massengill, Lloyd W ^a,b   Baze, Mark P ^a,c   Bhuva, Bharat L ^a,b   Witulski, Arthur F ^a,b   DasGupta, Sandeepan ^a,b   Sternberg, Andrew L ^a,b   Fleming, Patrick R ^a,b   Heath, Christopher C ^a,b   Alles, Michael L ^a,b  

^a IEEE   (United States)

^b VANDERBILT UNIVERSITY   (United States)

^c BOEING COMPANY   (United States)

Author keywords

Charge sharing; Cross section; DICE latch; Let threshold; n well potential collapse; Parasitic bipolar transistor; Radiation hardened by design; Single event circuit characterization; Single event upset

Indexed keywords

CHARGE SHARING; CROSS-SECTIONS; PARASITIC BIPOLAR TRANSISTORS; SINGLE EVENT CIRCUIT CHARACTERIZATION; SINGLE EVENT UPSET;

CHARGE TRANSFER; CIRCUIT SIMULATION; COMPUTER AIDED DESIGN; HEAVY IONS; RADIATION HARDENING; SENSITIVITY ANALYSIS;

CMOS INTEGRATED CIRCUITS;

EID: 37249055544     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2007.907989     Document Type: Conference Paper

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