Hardened by design techniques for implementing multiple-bit upset tolerant static memories

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 2786-2789

  Blum, Daniel R ^a   Delgado Frias, José G ^a  

^a Washington State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; LOGIC DESIGN;

MBU TOLERANT DESIGN; SPATIAL SEPARATION; TOLERANT MEMORY LATCHES;

DATA STORAGE EQUIPMENT;

EID: 34548834735     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.378631     Document Type: Conference Paper

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