Boxes: An engineering methodology for calculating soft error rates in SOI integrated circuits

IEEE Transactions on Nuclear Science

Volumn 53, Issue 6, 2006, Pages 3329-3335

  Fulkerson, David E ^a,b   Nelson, David K ^b   Carlson, Roy M ^b  

^a IEEE   (United States)

^b HONEYWELL TECHNOLOGY CENTER   (United States)

Author keywords

CREME96; Flip flop; Modeling; SEE; SEU; SOI; SPICE; SRAM

Indexed keywords

CRITICAL CHARGE; MODULAR REDUNDANCY; SOFT ERROR RATE (SER);

BIT ERROR RATE; COMPUTER SIMULATION; CRITICAL CURRENT DENSITY (SUPERCONDUCTIVITY); LOGIC GATES; SILICON ON INSULATOR TECHNOLOGY; STATIC RANDOM ACCESS STORAGE;

CMOS INTEGRATED CIRCUITS;

EID: 33846301002     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2006.886150     Document Type: Conference Paper

References (14)

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